vc/amd/fsp/cezanne: update UPD headers

The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.

The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.

BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.

Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

4 files changed, 109 insertions, 101 deletions

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index cb60c89816..083a82d90c 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -16,7 +16,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
 	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
-	mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
 	mcfg->serial_port_baudrate = get_uart_baudrate();
 	mcfg->serial_port_refclk = uart_platform_refclk();
 }
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index b117afb75c..ae51f9254a 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -5,7 +5,7 @@
 
 static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 {
-	scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index 960d0b4eb3..0ba9f8993e 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -12,61 +12,110 @@
 /** Fsp M Configuration
 **/
 typedef struct __packed {
-	/** Offset 0x0040**/	uint32_t                    pci_express_base_addr;
-	/** Offset 0x0044**/	uint32_t                    serial_port_base;
-	/** Offset 0x0048**/	uint32_t                    serial_port_use_mmio;
-	/** Offset 0x004C**/	uint32_t                    serial_port_stride;
-	/** Offset 0x0050**/	uint32_t                    serial_port_baudrate;
-	/** Offset 0x0054**/	uint32_t                    serial_port_refclk;
-	/** Offset 0x0058**/	uint32_t                    telemetry_vddcr_vdd_slope_mA;
-	/** Offset 0x005C**/	uint32_t                    telemetry_vddcr_vdd_slope2_mA;
-	/** Offset 0x0060**/	uint32_t                    telemetry_vddcr_vdd_slope3_mA;
-	/** Offset 0x0064**/	uint32_t                    telemetry_vddcr_vdd_slope4_mA;
-	/** Offset 0x0068**/	uint32_t                    telemetry_vddcr_vdd_slope5_mA;
-	/** Offset 0x006C**/	uint32_t                    telemetry_vddcr_vdd_offset;
-	/** Offset 0x0070**/	uint32_t                    telemetry_vddcr_soc_slope_mA;
-	/** Offset 0x0074**/	uint32_t                    telemetry_vddcr_soc_offset;
-	/** Offset 0x0078**/	uint8_t                     aa_mode_en;
-	/** Offset 0x0079**/	uint8_t                     unused2;
-	/** Offset 0x007A**/	uint8_t                     unused3;
-	/** Offset 0x007B**/	uint8_t                     unused4;
-	/** Offset 0x007C**/	uint32_t                    fast_ppt_limit_mW;
-	/** Offset 0x0080**/	uint32_t                    slow_ppt_limit_mW;
-	/** Offset 0x0084**/	uint32_t                    slow_ppt_time_constant_s;
-	/** Offset 0x0088**/	uint32_t                    psi0_current_limit_mA;
-	/** Offset 0x008C**/	uint32_t                    psi0_soc_current_limit_mA;
-	/** Offset 0x0090**/	uint32_t                    thermctl_limit_degreeC;
-	/** Offset 0x0094**/	uint32_t                    vrm_maximum_current_limit_mA;
-	/** Offset 0x0098**/	uint32_t                    vrm_soc_maximum_current_limit_mA;
-	/** Offset 0x009C**/	uint32_t                    sustained_power_limit_mW;
-	/** Offset 0x00A0**/	uint32_t                    stapm_time_constant_s;
-	/** Offset 0x00A4**/	uint32_t                    prochot_l_deassertion_ramp_time_ms;
-	/** Offset 0x00A8**/	uint32_t                    vrm_current_limit_mA;
-	/** Offset 0x00AC**/	uint32_t                    vrm_soc_current_limit_mA;
-	/** Offset 0x00B0**/	uint32_t                    vddcr_soc_voltage_margin_mV;
-	/** Offset 0x00B4**/	uint32_t                    vddcr_vdd_voltage_margin_mV;
-	/** Offset 0x00B8**/	uint32_t                    smu_feature_control_defines;
-	/** Offset 0x00BC**/	uint32_t                    smu_feature_control_defines_ext;
-	/** Offset 0x00C0**/	uint8_t                     sb_tsi_alert_comparator_mode_en;
-	/** Offset 0x00C1**/	uint8_t                     system_config;
-	/** Offset 0x00C2**/	uint8_t                     core_dldo_bypass;
-	/** Offset 0x00C3**/	uint8_t                     min_soc_vid_offset;
-	/** Offset 0x00C4**/	uint8_t                     aclk_dpm0_freq_400MHz;
-	/** Offset 0x00C5**/	uint8_t                     unused5;
-	/** Offset 0x00C6**/	uint8_t                     unused6;
-	/** Offset 0x00C7**/	uint8_t                     sata_enable;
-	/** Offset 0x00C8**/	uint32_t                    tseg_size;
-	/** Offset 0x00CC**/	uint8_t                     pspp_policy;
-	/** Offset 0x00CD**/	uint8_t                     audio_soundwire;
-	/** Offset 0x00CE**/	uint8_t                     hd_audio_enable;
-	/** Offset 0x00CF**/	uint8_t                     unused9;
-	/** Offset 0x00D0**/	uint32_t                    bert_size;
-	/** Offset 0x00D4**/	uint8_t                     UnusedUpdSpace0;
-	/** Offset 0x00D5**/	uint8_t                     ccx_down_core_mode;
-	/** Offset 0x00D6**/	uint8_t                     ccx_disable_smt;
-	/** Offset 0x00D7**/	uint8_t                     UnusedUpdSpace1[41];
-	/** Offset 0x0100**/	uint16_t                    Reserved100;
-	/** Offset 0x0102**/	uint16_t                    UpdTerminator;
+	/** Offset 0x0040**/	uint32_t                    bert_size;
+	/** Offset 0x0044**/	uint32_t                    tseg_size;
+	/** Offset 0x0048**/	uint32_t                    pci_express_base_addr;
+	/** Offset 0x004C**/	uint8_t                     misc_reserved[32];
+	/** Offset 0x006C**/	uint32_t                    serial_port_base;
+	/** Offset 0x0070**/	uint32_t                    serial_port_use_mmio;
+	/** Offset 0x0074**/	uint32_t                    serial_port_baudrate;
+	/** Offset 0x0078**/	uint32_t                    serial_port_refclk;
+	/** Offset 0x007C**/	uint32_t                    serial_reserved;
+	/** Offset 0x0080**/	uint8_t                     dxio_descriptor0[52];
+	/** Offset 0x00B4**/	uint8_t                     dxio_descriptor1[52];
+	/** Offset 0x00E8**/	uint8_t                     dxio_descriptor2[52];
+	/** Offset 0x011C**/	uint8_t                     dxio_descriptor3[52];
+	/** Offset 0x0150**/	uint8_t                     dxio_descriptor4[52];
+	/** Offset 0x0184**/	uint8_t                     dxio_descriptor5[52];
+	/** Offset 0x01B8**/	uint8_t                     dxio_descriptor6[52];
+	/** Offset 0x01EC**/	uint8_t                     dxio_descriptor7[52];
+	/** Offset 0x0220**/	uint8_t                     dxio_descriptor8[52];
+	/** Offset 0x0254**/	uint8_t                     dxio_descriptor9[52];
+	/** Offset 0x0288**/	uint8_t                     dxio_descriptor10[52];
+	/** Offset 0x02BC**/	uint8_t                     dxio_descriptor11[52];
+	/** Offset 0x02F0**/	uint8_t                     dxio_descriptor12[52];
+	/** Offset 0x0324**/	uint8_t                     dxio_descriptor13[52];
+	/** Offset 0x0358**/	uint8_t                     pcie_reserved[52];
+	/** Offset 0x038C**/	uint32_t                    ddi_descriptor0;
+	/** Offset 0x0390**/	uint32_t                    ddi_descriptor1;
+	/** Offset 0x0394**/	uint32_t                    ddi_descriptor2;
+	/** Offset 0x0398**/	uint32_t                    ddi_descriptor3;
+	/** Offset 0x039C**/	uint32_t                    ddi_descriptor4;
+	/** Offset 0x03A0**/	uint8_t                     ddi_reserved[6];
+	/** Offset 0x03A6**/	uint8_t                     ccx_down_core_mode;
+	/** Offset 0x03A7**/	uint8_t                     ccx_disable_smt;
+	/** Offset 0x03A8**/	uint8_t                     ccx_reserved[32];
+	/** Offset 0x03C8**/	uint8_t                     stt_control;
+	/** Offset 0x03C9**/	uint8_t                     stt_pcb_sensor_count;
+	/** Offset 0x03CA**/	uint16_t                    stt_min_limit;
+	/** Offset 0x03CC**/	uint16_t                    stt_m1;
+	/** Offset 0x03CE**/	uint16_t                    stt_m2;
+	/** Offset 0x03D0**/	uint16_t                    stt_m3;
+	/** Offset 0x03D2**/	uint16_t                    stt_m4;
+	/** Offset 0x03D4**/	uint16_t                    stt_m5;
+	/** Offset 0x03D6**/	uint16_t                    stt_m6;
+	/** Offset 0x03D8**/	uint16_t                    stt_c_apu;
+	/** Offset 0x03DA**/	uint16_t                    stt_c_gpu;
+	/** Offset 0x03DC**/	uint16_t                    stt_c_hs2;
+	/** Offset 0x03DE**/	uint16_t                    stt_alpha_apu;
+	/** Offset 0x03E0**/	uint16_t                    stt_alpha_gpu;
+	/** Offset 0x03E2**/	uint16_t                    stt_alpha_hs2;
+	/** Offset 0x03E4**/	uint16_t                    stt_skin_temp_apu;
+	/** Offset 0x03E6**/	uint16_t                    stt_skin_temp_gpu;
+	/** Offset 0x03E8**/	uint16_t                    stt_skin_temp_hs2;
+	/** Offset 0x03EA**/	uint16_t                    stt_error_coeff;
+	/** Offset 0x03EC**/	uint16_t                    stt_error_rate_coefficient;
+	/** Offset 0x03EE**/	uint8_t                     stapm_control;
+	/** Offset 0x03EF**/	uint8_t                     stapm_boost;
+	/** Offset 0x03F0**/	uint8_t                     smartshift_enable;
+	/** Offset 0x03F1**/	uint32_t                    apu_only_sppt_limit;
+	/** Offset 0x03F5**/	uint32_t                    sustained_power_limit;
+	/** Offset 0x03F9**/	uint32_t                    fast_ppt_limit;
+	/** Offset 0x03FD**/	uint32_t                    slow_ppt_limit;
+	/** Offset 0x0401**/	uint8_t                     system_configuration;
+	/** Offset 0x0402**/	uint8_t                     cppc_ctrl;
+	/** Offset 0x0403**/	uint8_t                     cppc_perf_limit_max_range;
+	/** Offset 0x0404**/	uint8_t                     cppc_perf_limit_min_range;
+	/** Offset 0x0405**/	uint8_t                     cppc_epp_max_range;
+	/** Offset 0x0406**/	uint8_t                     cppc_epp_min_range;
+	/** Offset 0x0407**/	uint8_t                     cppc_preferred_cores;
+	/** Offset 0x0408**/	uint8_t                     smu_soc_tuning_reserved[20];
+	/** Offset 0x041C**/	uint8_t                     iommu_support;
+	/** Offset 0x041D**/	uint8_t                     pspp_policy;
+	/** Offset 0x041E**/	uint8_t                     enable_nb_azalia;
+	/** Offset 0x041F**/	uint8_t                     audio_io_ctl;
+	/** Offset 0x0420**/	uint8_t                     pdm_mic_selection;
+	/** Offset 0x0421**/	uint8_t                     nbio_reserved[32];
+	/** Offset 0x0441**/	uint32_t                    emmc0_mode;
+	/** Offset 0x0445**/	uint16_t                    emmc0_init_khz_preset;
+	/** Offset 0x0447**/	uint8_t                     emmc0_sdr104_hs400_driver_strength;
+	/** Offset 0x0448**/	uint8_t                     emmc0_ddr50_driver_strength;
+	/** Offset 0x0449**/	uint8_t                     emmc0_sdr50_driver_strength;
+	/** Offset 0x044A**/	uint8_t                     fch_usb_version_major;
+	/** Offset 0x044B**/	uint8_t                     fch_usb_version_minor;
+	/** Offset 0x044C**/	uint8_t                     fch_usb_2_port0_phy_tune[9];
+	/** Offset 0x0455**/	uint8_t                     fch_usb_2_port1_phy_tune[9];
+	/** Offset 0x045E**/	uint8_t                     fch_usb_2_port2_phy_tune[9];
+	/** Offset 0x0467**/	uint8_t                     fch_usb_2_port3_phy_tune[9];
+	/** Offset 0x0470**/	uint8_t                     fch_usb_2_port4_phy_tune[9];
+	/** Offset 0x0479**/	uint8_t                     fch_usb_2_port5_phy_tune[9];
+	/** Offset 0x0482**/	uint8_t                     fch_usb_2_port6_phy_tune[9];
+	/** Offset 0x048B**/	uint8_t                     fch_usb_2_port7_phy_tune[9];
+	/** Offset 0x0494**/	uint8_t                     fch_usb_device_removable;
+	/** Offset 0x0495**/	uint8_t                     fch_usb_3_port_force_gen1;
+	/** Offset 0x0496**/	uint8_t                     fch_usb_u3_rx_det_wa_enable;
+	/** Offset 0x0497**/	uint8_t                     fch_usb_u3_rx_det_wa_portmap;
+	/** Offset 0x0498**/	uint8_t                     fch_usb_early_debug_select_enable;
+	/** Offset 0x0499**/	uint32_t                    xhci_oc_pin_select;
+	/** Offset 0x049D**/	uint8_t                     xhci0_force_gen1;
+	/** Offset 0x049E**/	uint8_t                     xhci_sparse_mode_enable;
+	/** Offset 0x049F**/	uint32_t                    gnb_ioapic_base;
+	/** Offset 0x04A3**/	uint8_t                     gnb_ioapic_id;
+	/** Offset 0x04A4**/	uint8_t                     fch_ioapic_id;
+	/** Offset 0x04A5**/	uint8_t                     sata_enable;
+	/** Offset 0x04A6**/	uint8_t                     fch_reserved[32];
+	/** Offset 0x04C6**/	uint8_t                     UnusedUpdSpace0[58];
+	/** Offset 0x0500**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
index 7025485e0c..3ac52c097f 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
@@ -10,50 +10,10 @@
 #include <FspUpd.h>
 
 typedef struct __packed {
-	/** Offset 0x0020**/	uint32_t                    emmc0_mode;
-	/** Offset 0x0024**/	uint16_t                    emmc0_init_khz_preset;
-	/** Offset 0x0026**/	uint8_t                     emmc0_sdr104_hs400_driver_strength;
-	/** Offset 0x0027**/	uint8_t                     emmc0_ddr50_driver_strength;
-	/** Offset 0x0028**/	uint8_t                     emmc0_sdr50_driver_strength;
-	/** Offset 0x0029**/	uint8_t                     unused0[7];
-	/** Offset 0x0030**/	uint8_t                     dxio_descriptor0[16];
-	/** Offset 0x0040**/	uint8_t                     dxio_descriptor1[16];
-	/** Offset 0x0050**/	uint8_t                     dxio_descriptor2[16];
-	/** Offset 0x0060**/	uint8_t                     dxio_descriptor3[16];
-	/** Offset 0x0070**/	uint8_t                     dxio_descriptor4[16];
-	/** Offset 0x0080**/	uint8_t                     dxio_descriptor5[16];
-	/** Offset 0x0090**/	uint8_t                     dxio_descriptor6[16];
-	/** Offset 0x00A0**/	uint8_t                     dxio_descriptor7[16];
-	/** Offset 0x00B0**/	uint8_t                     unused1[16];
-	/** Offset 0x00C0**/	uint32_t                    ddi_descriptor0;
-	/** Offset 0x00C4**/	uint32_t                    ddi_descriptor1;
-	/** Offset 0x00C8**/	uint32_t                    ddi_descriptor2;
-	/** Offset 0x00CC**/	uint32_t                    ddi_descriptor3;
-	/** Offset 0x00D0**/	uint8_t                     unused2[16];
-	/** Offset 0x00E0**/	uint8_t                     fch_usb_version_major;
-	/** Offset 0x00E1**/	uint8_t                     fch_usb_version_minor;
-	/** Offset 0x00E2**/	uint8_t                     fch_usb_2_port0_phy_tune[9];
-	/** Offset 0x00EB**/	uint8_t                     fch_usb_2_port1_phy_tune[9];
-	/** Offset 0x00F4**/	uint8_t                     fch_usb_2_port2_phy_tune[9];
-	/** Offset 0x00FD**/	uint8_t                     fch_usb_2_port3_phy_tune[9];
-	/** Offset 0x0106**/	uint8_t                     fch_usb_2_port4_phy_tune[9];
-	/** Offset 0x010F**/	uint8_t                     fch_usb_2_port5_phy_tune[9];
-	/** Offset 0x0118**/	uint8_t                     fch_usb_device_removable;
-	/** Offset 0x0119**/	uint8_t                     fch_usb_3_port_force_gen1;
-	/** Offset 0x011A**/	uint8_t                     fch_usb_u3_rx_det_wa_enable;
-	/** Offset 0x011B**/	uint8_t                     fch_usb_u3_rx_det_wa_portmap;
-	/** Offset 0x011C**/	uint8_t                     fch_usb_early_debug_select_enable;
-	/** Offset 0x011D**/	uint8_t                     unused3;
-	/** Offset 0x011E**/	uint32_t                    xhci_oc_pin_select;
-	/** Offset 0x0122**/	uint8_t                     xhci0_force_gen1;
-	/** Offset 0x0123**/	uint8_t                     xhci_sparse_mode_enable;
-	/** Offset 0x0124**/	uint32_t                    gnb_ioapic_base;
-	/** Offset 0x0128**/	uint8_t                     gnb_ioapic_id;
-	/** Offset 0x0129**/	uint8_t                     fch_ioapic_id;
-	/** Offset 0x012A**/	uint8_t                     UnusedUpdSpace0[6];
-	/** Offset 0x0130**/	uint32_t                    vbios_buffer_addr;
-	/** Offset 0x0134**/    uint8_t                     UnusedUpdSpace1[28];
-	/** Offset 0x0150**/	uint16_t                    UpdTerminator;
+	/** Offset 0x0020**/	uint32_t                    vbios_buffer;
+	/** Offset 0x0024**/	uint64_t                    gop_reserved;
+	/** Offset 0x002C**/	uint32_t                    reserved1;
+	/** Offset 0x0030**/	uint16_t                    UpdTerminator;
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration