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authorFelix Held <felix-coreboot@felixheld.de>2021-01-25 18:41:35 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-27 00:29:01 +0000
commit68a1cb58c0a751803c31897526c3efc5b4835f13 (patch)
tree24145ab0ba7aab071c61db89a66bef098f9e96df
parentc81509c71d47550accb509c260d945ef27cf7eef (diff)
downloadcoreboot-68a1cb58c0a751803c31897526c3efc5b4835f13.tar.xz
soc/amd/common/block/smbus: remove stale comment
The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/amd/common/block/smbus/sm.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c
index 80a11848f5..1ec2730561 100644
--- a/src/soc/amd/common/block/smbus/sm.c
+++ b/src/soc/amd/common/block/smbus/sm.c
@@ -9,11 +9,6 @@
#include <arch/ioapic.h>
#include <soc/southbridge.h>
-/*
-* The southbridge enables all USB controllers by default in SMBUS Control.
-* The southbridge enables SATA by default in SMBUS Control.
-*/
-
static void sm_init(struct device *dev)
{
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);