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authorDuncan Laurie <dlaurie@google.com>2018-12-05 12:51:23 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-07 11:18:43 +0000
commit695f2feaf8f9dd7e77749cdafbd6422fffc2be3e (patch)
tree81d4ecf9fc8535ca3b381cbc946460ea62b25860
parent8440bf7114dbe7777fb0d0b12ec6725bf362f174 (diff)
downloadcoreboot-695f2feaf8f9dd7e77749cdafbd6422fffc2be3e.tar.xz
soc/intel/cannonlake: Fix I2C clock input
The input clock for the I2C controllers was set at 133MHz but should really be 216MHz according to the kernel: https://patchwork.kernel.org/patch/10408729/ "Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C than Sunrisepoint which uses 120 MHz. Preliminary information was that both share the same clock rate but actual silicon implements elevated rate for better support for 3.4 MHz high-speed I2C." This change was tested on a sarien board where an I2C trackpad that was measuring ~700MHz on I2C and is now measuring ~380MHz. Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30061 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 78c6dfe62c..9e007b656e 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -197,7 +197,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
- default 133
+ default 216
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int