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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-04-29 19:49:25 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2020-05-04 22:45:48 +0000 |
| commit | 6ad8352a3de78e2f6869cc7fbc4274057fcffd4a (patch) | |
| tree | 0ceef937dc4bf3c7ebf607aa0fbeb3c08f42dee7 | |
| parent | e7a083ec3dc0d7696cf6a0eda03dac67d6936834 (diff) | |
| download | coreboot-6ad8352a3de78e2f6869cc7fbc4274057fcffd4a.tar.xz | |
src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M
Due to refactoring of Serial IO code in FSP v3163 onwards we need to
set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart
initialization is skipped in FSP. This makes sure that SerialIo
initialization in coreboot is not changed by FSP.
BUG=b:155315876
BRANCH=none
TEST=build and boot tglrvp/ripto/volteer and check UART debug logs
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 022cd830c9..e4f6e824c1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -82,6 +82,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, } m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); |