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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-05 08:39:57 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-28 08:53:30 +0000
commit6c7441f5e6e667b6602aa12832a52894cf06dd89 (patch)
tree67f191e557a2266d5adc14c6cbf6364f61adaff8
parent47d58e5df0a5d1a96e64408c3c9384024d5ddaa3 (diff)
downloadcoreboot-6c7441f5e6e667b6602aa12832a52894cf06dd89.tar.xz
cpu/x86: Rename __protected_start symbol
It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/cpu/x86/entry16.S2
-rw-r--r--src/cpu/x86/entry32.S9
-rw-r--r--src/drivers/amd/agesa/cache_as_ram.S2
-rw-r--r--src/soc/amd/common/block/cpu/car/cache_as_ram.S2
-rw-r--r--src/soc/amd/common/block/cpu/noncar/pre_c.S2
5 files changed, 9 insertions, 8 deletions
diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S
index 1ecd6ed422..501d01d3e4 100644
--- a/src/cpu/x86/entry16.S
+++ b/src/cpu/x86/entry16.S
@@ -125,7 +125,7 @@ _start16bit:
movl %ebp, %eax
/* Now that we are in protected mode jump to a 32 bit code segment. */
- ljmpl $ROM_CODE_SEG, $__protected_start
+ ljmpl $ROM_CODE_SEG, $bootblock_protected_mode_entry
/**
* The gdt is defined in gdt_init.S, it has a 4 Gb code segment
diff --git a/src/cpu/x86/entry32.S b/src/cpu/x86/entry32.S
index 32f61ad261..639ab36a57 100644
--- a/src/cpu/x86/entry32.S
+++ b/src/cpu/x86/entry32.S
@@ -25,8 +25,9 @@
*/
.align 4
-.globl __protected_start
-__protected_start:
+.globl bootblock_protected_mode_entry
+bootblock_protected_mode_entry:
+
/* Save the BIST value */
movl %eax, %ebp
@@ -54,14 +55,14 @@ debug_spinloop:
jz debug_spinloop
#endif
-bootblock_protected_mode_entry:
-
#if !CONFIG(USE_MARCH_586)
/* MMX registers required here */
/* BIST result in eax */
movd %eax, %mm0
+__timestamp:
+
/* Get an early timestamp */
rdtsc
movd %eax, %mm1
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 33940cb489..1e15eda017 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -26,7 +26,7 @@ _cache_as_ram_setup:
/*
* on entry:
* mm0: BIST (ignored)
- * mm2_mm1: timestamp at bootblock_protected_mode_entry
+ * mm2_mm1: timestamp
*/
bootblock_pre_c_entry:
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 6282d7e571..251e23aaad 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -21,7 +21,7 @@ _cache_as_ram_setup:
/*
* on entry:
* mm0: BIST (ignored)
- * mm2_mm1: timestamp at bootblock_protected_mode_entry
+ * mm2_mm1: timestamp
*/
.global bootblock_pre_c_entry
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index 520e3c08b0..5c16c29c8f 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -18,7 +18,7 @@ bootblock_resume_entry:
/*
* on entry:
* mm0: BIST (ignored)
- * mm2_mm1: timestamp at bootblock_protected_mode_entry
+ * mm2_mm1: timestamp
*/
.global bootblock_pre_c_entry