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authorDuncan Laurie <dlaurie@chromium.org>2013-08-08 16:28:41 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 12:02:43 +0100
commit727b5455fbdd3003005da83039f92c96354b53a2 (patch)
treeac0117d905bc9523f423e2c404e0193df7d1d780
parent7e1c83e31bdd4b0aeebb2ed0916959a472c2369f (diff)
downloadcoreboot-727b5455fbdd3003005da83039f92c96354b53a2.tar.xz
Add a specific post code for S3 resume failures
If the firwmare is flashed and the MRC cache is blown away then it is not possible to resume. Right now this can be inferred from the event log but it can be made very clear by adding a unique post code for this event. 1) boot falco 2) flash firmware 3) suspend and then resume 4) check for post code 0xef in log 0 | 2013-08-08 16:27:47 | Log area cleared | 4096 1 | 2013-08-08 16:27:47 | ACPI Enter | S3 2 | 2013-08-08 16:27:55 | System boot | 48 3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure 4 | 2013-08-08 16:27:55 | System Reset 5 | 2013-08-08 16:27:55 | ACPI Wake | S5 Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
-rw-r--r--src/include/console/post_codes.h8
-rw-r--r--src/northbridge/intel/haswell/raminit.c4
2 files changed, 11 insertions, 1 deletions
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index df1d5e8837..0310db3958 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -229,6 +229,14 @@
#define POST_DEAD_CODE 0xee
/**
+ * \brief Resume from suspend failed
+ *
+ * This post code is sent when the firmware is expected to resume it is
+ * unable to do so.
+ */
+#define POST_RESUME_FAILURE 0xef
+
+/**
* \brief Final code before OS resumes
*
* Called right before jumping to the OS resume vector.
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index a90b360116..e916c5e8a5 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -156,7 +156,9 @@ void sdram_initialize(struct pei_data *pei_data)
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
- printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
+ post_code(POST_RESUME_FAILURE);
+ printk(BIOS_DEBUG, "Giving up in sdram_initialize: "
+ "No MRC data\n");
outb(0x6, 0xcf9);
while(1) {
hlt();