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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-28 02:12:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-31 06:42:49 +0000 |
| commit | 764b987a6f93a64f18b1557e1591fc2afe47110c (patch) | |
| tree | e97eebd3199373d82bfeaaa53747a1d21d49c613 | |
| parent | 82a0a63f99a7c9e9afaf7fc6b85a93ef75e480cf (diff) | |
| download | coreboot-764b987a6f93a64f18b1557e1591fc2afe47110c.tar.xz | |
mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree
BUG=b:149970243
BRANCH=zork
Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 4413857cbb..16206439ee 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -180,6 +180,15 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end |