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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-22 08:57:40 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-27 15:44:58 +0000
commit78f52fb7d6cdc3bceef0a9a7c411253e136e5626 (patch)
tree09944a96d5f620828e9199037bf9fbcdc00e15ac
parentb04405ff766db9b4d0d6665b28d4860788fb6889 (diff)
downloadcoreboot-78f52fb7d6cdc3bceef0a9a7c411253e136e5626.tar.xz
soc/amd/stoneyridge: Change set_sb_nvs_final()
Change-Id: I0de8033bae8c1dcfbc6fd7655ba748a3514e74e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c45
1 files changed, 25 insertions, 20 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index feb25f1e09..11791f2b62 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -417,32 +417,33 @@ void southbridge_init(void *chip_info)
acpi_clear_pm_gpe_status();
}
-static void set_sb_final_nvs(void)
+static void set_sb_aoac(struct aoac_devs *aoac)
{
- uintptr_t amdfw_rom;
- uintptr_t xhci_fw;
- uintptr_t fwaddr;
- size_t fwsize;
const struct device *sd, *sata;
- struct global_nvs *gnvs = acpi_get_gnvs();
- if (gnvs == NULL)
- return;
+ aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0);
+ aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1);
+ aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2);
+ aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3);
+ aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0);
+ aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1);
+ aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2);
+ aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3);
- gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0);
- gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1);
- gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2);
- gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3);
- gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0);
- gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1);
- gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2);
- gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3);
/* Rely on these being in sync with devicetree */
sd = pcidev_path_on_root(SD_DEVFN);
- gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0;
+ aoac->sd_e = sd && sd->enabled ? 1 : 0;
sata = pcidev_path_on_root(SATA_DEVFN);
- gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0;
- gnvs->aoac.espi = 1;
+ aoac->st_e = sata && sata->enabled ? 1 : 0;
+ aoac->espi = 1;
+}
+
+static void set_sb_gnvs(struct global_nvs *gnvs)
+{
+ uintptr_t amdfw_rom;
+ uintptr_t xhci_fw;
+ uintptr_t fwaddr;
+ size_t fwsize;
amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX);
xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET));
@@ -468,7 +469,11 @@ void southbridge_final(void *chip_info)
restored_power = PM_RESTORE_S0_IF_PREV_S0;
pm_write8(PM_RTC_SHADOW, restored_power);
- set_sb_final_nvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
+ if (gnvs) {
+ set_sb_aoac(&gnvs->aoac);
+ set_sb_gnvs(gnvs);
+ }
}
/*