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authorArchana Patni <archana.patni@intel.com>2015-10-08 01:42:07 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-10-27 15:20:04 +0100
commit7d40e969e1bf5c333524e56ae22b6e25acd5b034 (patch)
tree6cf9bfc5ee600bf88c9ed346e36b4a77cbea67a5
parent20ffe1944ceb99c2ff11ea20f3343a8adb137639 (diff)
downloadcoreboot-7d40e969e1bf5c333524e56ae22b6e25acd5b034.tar.xz
intel/kunimitsu: csme: program sml gpios for csme power gating
For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive. The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables. SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are now configured as GPIOs - input and deep. With this change, the SMT blocks are properly power gating. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for Kunimitsu, boot on FAB3. Change-Id: I16b31a8d5c3c9df0f37df15c751c5a0978ac0feb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2913a75969008583f454a4bfc9da2156266548b Original-Change-Id: I00dca84a3f6ba7bda4ca1c206b49ff81482279a5 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306391 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12161 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rwxr-xr-xsrc/mainboard/intel/kunimitsu/gpio.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 1441738a83..3c4c127fa0 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -101,13 +101,13 @@ static const struct pad_config gpio_table[] = {
/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
-/* SM1ALERT# */ /* GPP_B23 */
+/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),
-/* SML0DATA */ /* GPP_C4 */
-/* SML0ALERT# */ /* GPP_C5 */
+/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),
/* UART0_RXD */ /* GPP_C8 */