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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-07-27 13:12:03 +0300
committerAnton Kochkov <anton.kochkov@gmail.com>2012-08-01 10:58:44 +0200
commit7f189cc74eb0358149f892c32a9bfa7b831c83a3 (patch)
treeb54f67f797309300a23fa878ef5196416e21d39d
parent1ec5e744c63938aa75e80e8d7548d05e998660a2 (diff)
downloadcoreboot-7f189cc74eb0358149f892c32a9bfa7b831c83a3.tar.xz
Intel Sandybridge and UMA: use mmio_resource()
With SandyBridge northbridge code, uma_memory_size was reset to zero before variable MTRRs were set. This means MTRR setup routine did not previously create a un-cacheable hole for uma. Keep the behaviour that way, mmio_resource() has a prerequisuite that the new region does not overlap with any cacheable ram_resource(). The result is not optimal setup in the number of used MTRRs, but continue with this approach until MTRR algorithm is improved. Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1373 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0df85a7493..2d948eaaef 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -111,17 +111,18 @@ static void add_fixed_resources(struct device *dev, int index)
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
- printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
- "size=0x%llx\n", uma_memory_base, uma_memory_size);
- resource = new_resource(dev, index++);
- resource->base = (resource_t) uma_memory_base;
- resource->size = (resource_t) uma_memory_size;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- /* Clear these values here so they don't get used by MTRR code */
- uma_memory_base = 0;
- uma_memory_size = 0;
+ /* Using uma_resource() here would fail as base & size cannot
+ * be used as-is for a single MTRR. This would cause excessive
+ * use of MTRRs.
+ *
+ * Use of mmio_resource() instead does not create UC holes by using
+ * MTRRs, but making these regions uncacheable is taken care of by
+ * making sure they do not overlap with any ram_resource().
+ *
+ * The resources can be changed to use separate mmio_resource()
+ * calls after MTRR code is able to merge them wisely.
+ */
+ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "