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authorDavid Hendricks <dhendrix@chromium.org>2013-08-12 13:24:24 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 22:46:52 +0100
commit7f35bbb0d4c2993f227b83250c5c5df0d02139e3 (patch)
tree1926889ca50de266ed91ab20870dbd30d0fea7f8
parentb783d4585ff6c229ec76619c3f9666070e19359e (diff)
downloadcoreboot-7f35bbb0d4c2993f227b83250c5c5df0d02139e3.tar.xz
exynos5420: don't assume MPLL for i2c parent clock
This reads the clock select field for MUX_ACLK_66_SEL in the CLK_SRC_TOP1 register in order to obtain the source clock rate for I2C peripherals. Before we were always assuming that the source was the MPLL. Unfortunately not all fields in the CLK_SRC_TOPn registers are enumerated the same with regard to clock select. So this is just a one-off for now. This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f Reviewed-on: https://gerrit.chromium.org/gerrit/65611 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
-rw-r--r--src/cpu/samsung/exynos5420/clock.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index 783679a096..34d3fb58dc 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -231,7 +231,23 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
case PERIPH_ID_I2C8:
case PERIPH_ID_I2C9:
case PERIPH_ID_I2C10:
- sclk = get_pll_clk(MPLL);
+ /*
+ * I2C block parent clock selection is different from other
+ * peripherals, so we handle it all here.
+ * TODO: Add a helper function like with the peripheral clock
+ * select fields?
+ */
+ src = (readl(&clk->clk_src_top1) >> 8) & 0x3;
+ if (src == 0x0)
+ src = CPLL;
+ else if (src == 0x1)
+ src = DPLL;
+ else if (src == 0x2)
+ src = MPLL;
+ else
+ return -1;
+
+ sclk = get_pll_clk(src);
div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1;
return sclk / div;
default: