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authorAlexander Couzens <lynxis@fe80.eu>2016-03-09 03:13:45 +0100
committerMartin Roth <martinroth@google.com>2016-03-11 18:56:21 +0100
commit81c5c761b305dd62019759e5e39248b02c0af820 (patch)
tree25aa975422c72af95b419b5768e53749a06ff458
parent013accca7fb955dd04ee8a51d98e3d94a4941346 (diff)
downloadcoreboot-81c5c761b305dd62019759e5e39248b02c0af820.tar.xz
northbridge/intel: move mrc_cache definition into a common header
The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/northbridge/intel/common/mrc_cache.h15
-rw-r--r--src/northbridge/intel/fsp_sandybridge/northbridge.h4
-rw-r--r--src/northbridge/intel/haswell/haswell.h13
-rw-r--r--src/northbridge/intel/haswell/mrccache.c1
-rw-r--r--src/northbridge/intel/haswell/raminit.c1
-rw-r--r--src/northbridge/intel/nehalem/nehalem.h13
-rw-r--r--src/northbridge/intel/nehalem/raminit.c1
-rw-r--r--src/northbridge/intel/sandybridge/mrccache.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c1
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h13
11 files changed, 24 insertions, 40 deletions
diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h
new file mode 100644
index 0000000000..5c66ccc34a
--- /dev/null
+++ b/src/northbridge/intel/common/mrc_cache.h
@@ -0,0 +1,15 @@
+#ifndef NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H
+#define NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H
+
+#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
+
+struct mrc_data_container {
+ u32 mrc_signature; // "MRCD"
+ u32 mrc_data_size; // Actual total size of this structure
+ u32 mrc_checksum; // IP style checksum
+ u32 reserved; // For header alignment
+ u8 mrc_data[0]; // Variable size, platform/run time dependent.
+} __attribute__ ((packed));
+
+#endif /* NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H */
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index ab428c318f..a41b2cab6e 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -215,10 +215,6 @@ void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
-
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
-
#if !defined(__PRE_RAM__)
#include "gma.h"
int init_igd_opregion(igd_opregion_t *igd_opregion);
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 8a01edccd9..c560428a06 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -213,18 +213,7 @@ void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
-
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
-
-struct mrc_data_container {
- u32 mrc_signature; // "MRCD"
- u32 mrc_data_size; // Actual total size of this structure
- u32 mrc_checksum; // IP style checksum
- u32 reserved; // For header alignment
- u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
-
+struct mrc_data_container;
struct mrc_data_container *find_current_mrc_cache(void);
#if !defined(__PRE_RAM__)
#include "gma.h"
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index 7139930782..09bf73fcc7 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -20,6 +20,7 @@
#include <cbfs.h>
#include <fmap.h>
#include <ip_checksum.h>
+#include <northbridge/intel/common/mrc_cache.h>
#include <device/device.h>
#include <cbmem.h>
#include "pei_data.h"
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 92a453232b..4644f05e59 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -22,6 +22,7 @@
#include <cbfs.h>
#include <halt.h>
#include <ip_checksum.h>
+#include <northbridge/intel/common/mrc_cache.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
#include "raminit.h"
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index d15c7efbb6..a2536ccc26 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -593,18 +593,7 @@ void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
-
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
-
-struct mrc_data_container {
- u32 mrc_signature; // "MRCD"
- u32 mrc_data_size; // Actual total size of this structure
- u32 mrc_checksum; // IP style checksum
- u32 reserved; // For header alignment
- u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
-
+struct mrc_data_container;
struct mrc_data_container *find_current_mrc_cache(void);
#if !defined(__PRE_RAM__)
#include "gma.h"
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 4bc95ba27d..a5a627672a 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -40,6 +40,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
+#include <northbridge/intel/common/mrc_cache.h>
#endif
#if !REAL
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index 37bca8564b..f243c27464 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -24,6 +24,7 @@
#include <cbmem.h>
#include "pei_data.h"
#include "sandybridge.h"
+#include <northbridge/intel/common/mrc_cache.h>
#include <spi-generic.h>
#include <spi_flash.h>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 1527ec34cc..0b27fe5524 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -26,6 +26,7 @@
#include <ip_checksum.h>
#include <timestamp.h>
#include <pc80/mc146818rtc.h>
+#include <northbridge/intel/common/mrc_cache.h>
#include <device/pci_def.h>
#include <memory_info.h>
#include <smbios.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 162caf6107..c26f012ff3 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -24,6 +24,7 @@
#include <ip_checksum.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
+#include <northbridge/intel/common/mrc_cache.h>
#include <halt.h>
#include <timestamp.h>
#include "raminit.h"
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index ba8f8d9ae7..116e0a8c7f 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -235,18 +235,7 @@ struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);
#endif
-
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
-
-struct mrc_data_container {
- u32 mrc_signature; // "MRCD"
- u32 mrc_data_size; // Actual total size of this structure
- u32 mrc_checksum; // IP style checksum
- u32 reserved; // For header alignment
- u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
-
+struct mrc_data_container;
struct mrc_data_container *find_current_mrc_cache(void);
#if !defined(__PRE_RAM__)
#include "gma.h"