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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-10 22:17:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-11 14:25:46 +0000 |
| commit | 8273e13a115289c48beb7366cf7a03ccd8b5e108 (patch) | |
| tree | 27f7d79b8a56d6ea38ae99cb7c88b29504c353ca | |
| parent | 8355aa4de2096561e5a32e7e870da144c1881b14 (diff) | |
| download | coreboot-8273e13a115289c48beb7366cf7a03ccd8b5e108.tar.xz | |
intel/i945: Call fixup_i945_errata() only for mobile version
Per Mobile Intel ® 945 Express Chipset Family - Specification Update
Document Number: 309220-013 (page 15), the power saving optimization
Erratum is for Mobile Intel ® 945 Express Chipset family.
So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply
that function only for I945GM.
Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/northbridge/intel/i945/errata.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/romstage.c | 3 |
3 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c index 2b9b941aba..4d8b999d46 100644 --- a/src/northbridge/intel/i945/errata.c +++ b/src/northbridge/intel/i945/errata.c @@ -17,7 +17,7 @@ #include "i945.h" #include "raminit.h" -int fixup_i945_errata(void) +int fixup_i945gm_errata(void) { u32 reg32; diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index d417169c62..26a1f5024b 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -67,5 +67,5 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -int fixup_i945_errata(void); +int fixup_i945gm_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 6274e099c8..2333b7d79a 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -76,7 +76,8 @@ void mainboard_romstage_entry(void) mainboard_late_rcba_config(); /* Chipset Errata! */ - fixup_i945_errata(); + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + fixup_i945gm_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); |