diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-01-08 00:13:21 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:03:59 +0000 |
| commit | 83af733a47ad27cb4f37acf84b8cfe1cead0b949 (patch) | |
| tree | e8bacca9fb88f0ac74cf0218a05ec9b26641c265 | |
| parent | 2fd49721b17f9020c2b449aad778f011dae7bf46 (diff) | |
| download | coreboot-83af733a47ad27cb4f37acf84b8cfe1cead0b949.tar.xz | |
soc/intel/common/cse: Add description for macros
Below changes are done in the patch:
1. Remove unnecessary lining, and replace spaces with tabs
2. Add description for macros
3. Correct comment mentioned for wrapper #ifndef
TEST=Build and Boot hatch board
Change-Id: I630446234321e7998ab42f8506a58b16e9ce4eb0
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 751c01d565..bf829b0fe1 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -26,7 +26,7 @@ /* Global Reset Command ID */ #define MKHI_CBM_GLOBAL_RESET_REQ 0xb -/* RST Origin */ +/* Origin of Global Reset command */ #define GR_ORIGIN_BIOS_POST 0x2 /* HMRFPO Command Ids */ @@ -127,7 +127,6 @@ uint32_t me_read_config32(int offset); */ bool is_cse_enabled(void); - /* Makes the host ready to communicate with CSE*/ void set_host_ready(void); @@ -157,18 +156,20 @@ int send_hmrfpo_enable_msg(void); */ int send_hmrfpo_get_status_msg(void); +/* Fixed Address MEI Header's Host Address field value */ +#define BIOS_HOST_ADDR 0x00 -#define BIOS_HOST_ADDR 0x00 -#define HECI_MKHI_ADDR 0x07 +/* Fixed Address MEI Header's ME Address field value */ +#define HECI_MKHI_ADDR 0x07 /* Command GLOBAL_RESET_REQ Reset Types */ -#define GLOBAL_RESET 1 -#define HOST_RESET_ONLY 2 -#define CSE_RESET_ONLY 3 +#define GLOBAL_RESET 1 +#define HOST_RESET_ONLY 2 +#define CSE_RESET_ONLY 3 -/*HMRFPO Status types */ +/* HMRFPO Status types */ #define MKHI_HMRFPO_DISABLED 0 #define MKHI_HMRFPO_LOCKED 1 #define MKHI_HMRFPO_ENABLED 2 -#endif // SOC_INTEL_COMMON_MSR_H +#endif // SOC_INTEL_COMMON_CSE_H |