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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-10-28 02:48:25 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-10-29 11:19:34 +0000
commit84bf089f6a769a88db9717787eab078b00aaafb7 (patch)
tree88e13ce96e872788df99a41e833fd8f13dfe0b3c
parentc5f4a8c8f04f7c3eb3e11c9f3f5205983aba16fe (diff)
downloadcoreboot-84bf089f6a769a88db9717787eab078b00aaafb7.tar.xz
Documentation/mainboard: Add emulation/spike-riscv.md
Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
-rw-r--r--Documentation/mainboard/emulation/spike-riscv.md23
-rw-r--r--Documentation/mainboard/index.md6
-rw-r--r--src/mainboard/emulation/spike-riscv/Kconfig.name4
3 files changed, 29 insertions, 4 deletions
diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md
new file mode 100644
index 0000000000..55e87d9cc9
--- /dev/null
+++ b/Documentation/mainboard/emulation/spike-riscv.md
@@ -0,0 +1,23 @@
+# Spike RISC-V emulator
+
+[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.
+
+
+## Installation
+
+- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/>
+- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>,
+ which are necessary in order to have a serial console
+- Compile `riscv-fesvr` and then `riscv-isa-sim`
+
+
+## Building coreboot and running it in Spike
+
+- Configure coreboot and run `make` as usual
+- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
+ convert coreboot to an ELF that Spike can load
+- Run `spike -m1024 build/coreboot.elf`
+
+
+[Spike]: https://github.com/riscv/riscv-isa-sim
+[RISC-V]: https://riscv.org/
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index c346a3b8f0..c1e5262a98 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -10,6 +10,12 @@ This section contains documentation about coreboot on specific mainboards.
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
+## Emulation
+
+The boards in this section are not real mainboards, but emulators.
+
+- [Spike RISC-V emulator](emulation/spike-riscv.md)
+
## Foxconn
- [D41S](foxconn/d41s.md)
diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name
index 3a82ab1a66..17549c6ebb 100644
--- a/src/mainboard/emulation/spike-riscv/Kconfig.name
+++ b/src/mainboard/emulation/spike-riscv/Kconfig.name
@@ -1,7 +1,3 @@
config BOARD_EMULATION_SPIKE_RISCV
bool "SPIKE riscv"
help
- To run coreboot in spike:
- * run "make" as usual
- * util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
- * spike -m1024 build/coreboot.elf