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authorRaul E Rangel <rrangel@chromium.org>2018-05-11 11:08:08 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-05-14 07:34:51 +0000
commit8af20c6403d99c86e3c83fb9b53ec5bf7f9d2a78 (patch)
treed5a855a8a22427e02f3ee69cff0d1d11c94a0a0f
parentf3d99b6a657fe2bc3cff71956ab4f68fd1f287fe (diff)
downloadcoreboot-8af20c6403d99c86e3c83fb9b53ec5bf7f9d2a78.tar.xz
grunt: use stage cache when waking from S3
BUG=b:79154155 TEST=built and tested on grunt 31 entries total: 0:1st timestamp 20,917 900:calling AmdInitReset 87,525 (66,608) 901:back from AmdInitReset 98,318 (10,793) 902:calling AmdInitEarly 99,165 (847) 903:back from AmdInitEarly 139,619 (40,454) 5:start of verified boot 156,301 (16,682) 503:starting to initialize TPM 156,697 (396) 504:finished TPM initialization 186,107 (29,410) 505:starting to verify keyblock/preamble (RSA) 187,316 (1,209) 506:finished verifying keyblock/preamble (RSA) 208,000 (20,684) 507:starting to verify body (load+SHA2+RSA) 208,108 (108) 508:finished loading body (ignore for x86) 273,238 (65,130) 509:finished calculating body hash (SHA2) 290,364 (17,126) 510:finished verifying body signature (RSA) 294,236 (3,872) 511:starting TPM PCR extend 295,071 (835) 512:finished TPM PCR extend 320,512 (25,441) 513:starting locking TPM 320,514 (2) 514:finished locking TPM 332,081 (11,567) 6:end of verified boot 332,083 (2) 13:starting to load romstage 332,187 (104) 4:end of romstage 395,559 (63,372) 10:start of ramstage 395,999 (440) 916:calling AmdS3LateRestore 396,135 (136) 917:back from AmdS3LateRestore 428,066 (31,931) 30:device enumeration 428,087 (21) 40:device configuration 434,640 (6,553) 50:device enable 438,185 (3,545) 60:device initialization 439,565 (1,380) 70:device setup done 453,326 (13,761) 918:calling AmdS3FinalRestore 454,363 (1,037) 919:back from AmdS3FinalRestore 455,520 (1,157) 98:ACPI wake jump 467,541 (12,021) Total Time: 446,624 Change-Id: I326e81d3c987130e258c616c7c66dd82ddc0d942 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26219 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/common/block/pi/agesawrapper.c21
1 files changed, 17 insertions, 4 deletions
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index f72810fed9..436bf8f253 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -22,6 +22,7 @@
#include <delay.h>
#include <rules.h>
#include <rmodule.h>
+#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
#include <amdblocks/s3_resume.h>
@@ -559,10 +560,22 @@ static int agesa_locate_stage_file_ramstage(const char *name,
.prog = &prog,
};
- if (prog_locate(&prog))
- return -1;
- if (rmodule_stage_load(&rmod_agesa) < 0)
- return -1;
+ if (acpi_is_wakeup_s3() && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
+ printk(BIOS_INFO, "AGESA: Loading stage from cache\n");
+ // There is no way to tell if this succeeded.
+ stage_cache_load_stage(STAGE_REFCODE, &prog);
+ } else {
+ if (prog_locate(&prog))
+ return -1;
+
+ if (rmodule_stage_load(&rmod_agesa) < 0)
+ return -1;
+
+ if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
+ printk(BIOS_INFO, "AGESA: Saving stage to cache\n");
+ stage_cache_add(STAGE_REFCODE, &prog);
+ }
+ }
return rdev_chain(rdev, prog_rdev(&prog), 0,
region_device_sz(prog_rdev(&prog)));