AGESA f15: Remove f10 references

Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.

Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

13 files changed, 24 insertions, 51 deletions

diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
index c7101996f5..e2b58c8597 100644
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -24,7 +24,7 @@
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#include "northbridge/amd/agesa/family10/reset_test.h"
+#include "northbridge/amd/agesa/family15/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
 
diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h
index ac3c8182a3..794c005680 100644
--- a/src/mainboard/amd/dinar/rd890_cfg.h
+++ b/src/mainboard/amd/dinar/rd890_cfg.h
@@ -28,11 +28,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
 #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
 #define DEFAULT_HT_PATH		{0x0, 0x1}
+#else /* FAMILY10 */
+#define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
 #endif
 
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index b146afe0d6..e93e83e914 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -425,13 +425,4 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
  * This file include MUST occur AFTER the user option selection settings
  */
 
-/*
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
-  #define BLDOPT_REMOVE_FAMILY_10_SUPPORT         TRUE
-#endif
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
-  #define BLDOPT_REMOVE_FAMILY_15_SUPPORT         TRUE
-#endif
-*/
-
 #include "MaranelloInstall.h"
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
index 6607094281..0227c3f54d 100644
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
@@ -27,11 +27,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
 #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
 #define DEFAULT_HT_PATH		{0x0, 0x1}
+#else /* FAMILY10 */
+#define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
 #endif
 
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 79e045156f..031d0a2902 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -25,7 +25,7 @@
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family10/reset_test.h>
+#include <northbridge/amd/agesa/family15/reset_test.h>
 #include <nb_cimx.h>
 #include <sb_cimx.h>
 #include <superio/nuvoton/wpcm450/wpcm450.h>
diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h
index 6607094281..0227c3f54d 100644
--- a/src/mainboard/supermicro/h8scm/rd890_cfg.h
+++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h
@@ -27,11 +27,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
 #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
 #define DEFAULT_HT_PATH		{0x0, 0x1}
+#else /* FAMILY10 */
+#define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
 #endif
 
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index d4fdaf2eb0..5d8351d91e 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -25,7 +25,7 @@
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family10/reset_test.h>
+#include <northbridge/amd/agesa/family15/reset_test.h>
 #include <nb_cimx.h>
 #include <sb_cimx.h>
 #include <superio/nuvoton/wpcm450/wpcm450.h>
diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c
index e27ec163ee..7c5ea5a34a 100644
--- a/src/mainboard/tyan/s8226/buildOpts.c
+++ b/src/mainboard/tyan/s8226/buildOpts.c
@@ -425,13 +425,4 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
  * This file include MUST occur AFTER the user option selection settings
  */
 
-/*
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
-  #define BLDOPT_REMOVE_FAMILY_10_SUPPORT         TRUE
-#endif
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
-  #define BLDOPT_REMOVE_FAMILY_15_SUPPORT         TRUE
-#endif
-*/
-
 #include "SanMarinoInstall.h"
diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h
index 6607094281..0227c3f54d 100644
--- a/src/mainboard/tyan/s8226/rd890_cfg.h
+++ b/src/mainboard/tyan/s8226/rd890_cfg.h
@@ -27,11 +27,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
 #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
 #define DEFAULT_HT_PATH		{0x0, 0x1}
+#else /* FAMILY10 */
+#define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
 #endif
 
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index 5311a87a3b..220098dadd 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -25,7 +25,7 @@
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family10/reset_test.h>
+#include <northbridge/amd/agesa/family15/reset_test.h>
 #include <nb_cimx.h>
 #include <sb_cimx.h>
 #include <superio/winbond/common/winbond.h>
diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family15/amdfam10.h
index 27f78a3331..27f78a3331 100644
--- a/src/northbridge/amd/agesa/family10/amdfam10.h
+++ b/src/northbridge/amd/agesa/family15/amdfam10.h
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family15/reset_test.h
index 61de4d9895..61de4d9895 100644
--- a/src/northbridge/amd/agesa/family10/reset_test.h
+++ b/src/northbridge/amd/agesa/family15/reset_test.h
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 6b4d81a62a..88ed41cb41 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -49,13 +49,15 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
 }
 
 
-/* family 10 only, for reg > 0xFF */
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
-	IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
-static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
-				  u32 val)
+static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev,
+	u32 reg_pos, u32 mask, u32 val)
 {
 	u32 reg_old, reg;
+
+	/* family 10 only, for reg > 0xFF */
+	if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
+		return;
+
 	reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
 	reg &= ~mask;
 	reg |= val;
@@ -63,10 +65,6 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m
 		pci_write_config32(fam10_dev, reg_pos, reg);
 	}
 }
-#else
-#define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0)
-#endif
-
 
 /*
 * Compliant with CIM_33's ATINB_PrepareInit
@@ -222,8 +220,7 @@ void sr5650_htinit(void)
 		/* Enable Protocol checker */
 		set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
-	IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
 		/* HT3 mode, RPR 5.4.3 */
 		set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
 
@@ -269,7 +266,7 @@ void sr5650_htinit(void)
 		//set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
 
 		/* HT Buffer Allocation for Ganged Links!!! */
-#endif	/* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
+#endif	/* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
 	}
 
 }
@@ -301,8 +298,6 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void)
 	}
 }
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
-	IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
 void fam10_optimization(void)
 {
 	device_t cpu_f0, cpu_f2, cpu_f3;
@@ -310,6 +305,9 @@ void fam10_optimization(void)
 	msr_t msr;
 	u32 val;
 
+	if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
+		return;
+
 	printk(BIOS_INFO, "fam10_optimization()\n");
 	msr = rdmsr(0xC001001F);
 	msr.hi |= 1 << 14;	/* bit 46: EnableCf8ExtCfg */
@@ -329,9 +327,6 @@ void fam10_optimization(void)
 	/* TODO: HT Buffer Allocation for (un)Ganged Links */
 	/* rpr Table 5-11, 5-12 */
 }
-#else
-#define fam10_optimization() do {} while (0)
-#endif	/* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
 
 /*****************************************
 * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE