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authorAaron Durbin <adurbin@chromium.org>2013-01-15 15:34:08 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-18 18:50:37 +0100
commit8e345d4ca2a13ebdf9edf1071d7c4f03d084d143 (patch)
tree28712b91acfe7f1cccc840fa523e761c18d17c44
parent18af4d23f6b17827dda50d17d8dc9da5b2656eef (diff)
downloadcoreboot-8e345d4ca2a13ebdf9edf1071d7c4f03d084d143.tar.xz
haswell: lapic timer support
Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model to the switch statement. Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/cpu/x86/lapic/apic_timer.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index cd6e472494..b60da27256 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -62,6 +62,8 @@ static int set_timer_fsb(void)
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
+ case 0x3c: /* Haswell BCLK fixed at 100MHz */
+ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
timer_fsb = 100;
break;
default: