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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-09-27 16:44:40 -0600
committerMartin Roth <martinroth@google.com>2017-11-17 17:40:51 +0000
commit91b80416b700bbc40f282ba090b1f43d822f36fc (patch)
treea0ec150140a8a9a1be78e12ffc4a0c679c64cb8d
parent081851a9e470cb0236650fd0de33b2f5b0384a32 (diff)
downloadcoreboot-91b80416b700bbc40f282ba090b1f43d822f36fc.tar.xz
amd/stoneyridge: Enable SMI trap on SlpTyp
Program PMx08 to support SMIs when software writes the SlpTyp bit in the Pm1Control register. The southbridge needs to send the SMI message prior to the completion response of the I/O cycle. Also, disable sending the STPCLK message before the completion response. Disable the SlpTyp functionality, then enable the SMI source. BUG=b:65595850 Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 6ab06780c8..600b064f2d 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -42,6 +42,8 @@ void sb_enable(device_t dev)
static void sb_init_acpi_ports(void)
{
+ u32 reg;
+
/* We use some of these ports in SMM regardless of whether or not
* ACPI tables are generated. Enable these ports indiscriminately.
*/
@@ -57,6 +59,22 @@ static void sb_init_acpi_ports(void)
/* APMC - SMI Command Port */
pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+
+ /* SMI on SlpTyp requires sending SMI before completion
+ * response of the I/O write. The BKDG also specifies
+ * clearing ForceStpClkRetry for SMI trapping.
+ */
+ reg = pm_read32(PM_PCI_CTRL);
+ reg |= FORCE_SLPSTATE_RETRY;
+ reg &= ~FORCE_STPCLK_RETRY;
+ pm_write32(PM_PCI_CTRL, reg);
+
+ /* Disable SlpTyp feature */
+ reg = pm_read8(PM_RST_CTRL1);
+ reg &= ~SLPTYPE_CONTROL_EN;
+ pm_write8(PM_RST_CTRL1, reg);
+
+ configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
} else {
pm_write16(PM_ACPI_SMI_CMD, 0);
}