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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-02-19 17:52:29 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 12:46:50 +0000
commit94022a0abf044ef48bf1ca99851111c1dc08ded0 (patch)
tree949bd343995f92fb8d4038266beccae701b2a5b7
parent0868f964398e401c7c100627e6c2d713699772a0 (diff)
downloadcoreboot-94022a0abf044ef48bf1ca99851111c1dc08ded0.tar.xz
mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption. BUG=b:149289256 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
-rw-r--r--src/mainboard/google/drallion/variants/drallion/gpio.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index 85de17346a..d26abdb2be 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -184,9 +184,9 @@ static const struct pad_config gpio_table[] = {
/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */
/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
-/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */
+/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), /* CTLESS_DET# */
/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */
-/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */
+/* SD_CLK */ PAD_NC(GPP_G6, NONE), /* AUD_PWR_EN */
/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),