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authorRonald G. Minnich <rminnich@gmail.com>2006-04-27 17:37:23 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-04-27 17:37:23 +0000
commit94571a4767bff35961d8dd81a36752442ec7405d (patch)
treeb8c1715d7cb4dcba2dcf63f4bbae6cf2d2e1d9a9
parent3716427e7f63fd00e8117fca2027f2fe3a5bbf00 (diff)
downloadcoreboot-94571a4767bff35961d8dd81a36752442ec7405d.tar.xz
removing redundant and unneeded calls to functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/northbridge/amd/gx2/northbridge.c2
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c4
2 files changed, 5 insertions, 1 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 1dd4c9c7a3..55dc4acc18 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -418,7 +418,7 @@ static void enable_dev(struct device *dev)
northbridgeinit();
cpubug();
chipsetinit();
- setup_gx2();
+ //setup_gx2();
/* do this here for now -- this chip really breaks our device model */
setup_realmode_idt();
do_vsmbios();
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 0998a6af96..77a2dce6cd 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -544,18 +544,22 @@ northbridgeinit(void)
int i;
printk_debug("Enter %s\n", __FUNCTION__);
+/*
for(i = 0; gliutables[i]; i++)
GLIUInit(gliutables[i]);
GeodeLinkPriority();
+ */
/* Now that the descriptor to memory is set up.*/
/* The memory controller needs one read to synch it's lines before it can be used.*/
i = *(int *) 0;
GLPCIInit();
+/*
ClockGatingInit();
+ */
__asm__("FINIT\n");
/* CPUBugsFix -- called elsewhere */
printk_debug("Exit %s\n", __FUNCTION__);