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authorAngel Pons <th3fanbus@gmail.com>2020-10-23 20:39:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-27 10:05:35 +0000
commit99af210456d346187692e0b7b982b01c28006ab0 (patch)
tree6fc1fea67a0839f6ed714f859a8e4127ddf84a2c
parentce19f4f8ad069bf1ba85578ffb416e2a1eb9f1c9 (diff)
downloadcoreboot-99af210456d346187692e0b7b982b01c28006ab0.tar.xz
mb/google/auron: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/auron/devicetree.cb115
-rw-r--r--src/mainboard/google/auron/variants/auron_paine/overridetree.cb12
-rw-r--r--src/mainboard/google/auron/variants/auron_yuna/overridetree.cb12
-rw-r--r--src/mainboard/google/auron/variants/buddy/overridetree.cb42
-rw-r--r--src/mainboard/google/auron/variants/gandof/overridetree.cb12
-rw-r--r--src/mainboard/google/auron/variants/lulu/overridetree.cb12
-rw-r--r--src/mainboard/google/auron/variants/samus/overridetree.cb42
7 files changed, 131 insertions, 116 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index a3097624fe..09593b7b53 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -15,27 +15,6 @@ chip soc/intel/broadwell
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- register "sata_port_map" = "0x1"
- register "sio_acpi_mode" = "1"
-
- # Force enable ASPM for PCIe Port1
- register "pcie_port_force_aspm" = "0x01"
-
- # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013c0000"
-
register "s0ix_enable" = "1"
device cpu_cluster 0 on
@@ -46,40 +25,64 @@ chip soc/intel/broadwell
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 off end # SMBus
- device pci 1f.6 on end # Thermal
+
+# chip soc/intel/broadwell/pch
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "1"
+
+ # Force enable ASPM for PCIe Port1
+ register "pcie_port_force_aspm" = "0x01"
+
+ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013c0000"
+
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
+# end
end
end
diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index 60aef30a58..dc70085dd0 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
-
- device domain 0 on end
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+# end
+ end
end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index da80fecba8..b46e34cf83 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x7"
- register "sata_port1_gen3_dtle" = "0x5"
-
- device domain 0 on end
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x7"
+ register "sata_port1_gen3_dtle" = "0x5"
+# end
+ end
end
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index f14896425a..45229bad6d 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -7,32 +7,34 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- register "sata_devslp_disable" = "0x1"
+ register "s0ix_enable" = "0"
- register "sio_i2c0_voltage" = "1" # 1.8V
- register "sio_i2c1_voltage" = "0" # 3.3V
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ register "sata_devslp_disable" = "0x1"
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
+ register "sio_i2c0_voltage" = "1" # 1.8V
+ register "sio_i2c1_voltage" = "0" # 3.3V
- # Force enable ASPM for PCIe Port 5
- register "pcie_port_force_aspm" = "0x10"
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
- # Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ # Force enable ASPM for PCIe Port 5
+ register "pcie_port_force_aspm" = "0x10"
- # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x01220000"
+ # Enable port coalescing
+ register "pcie_port_coalesce" = "1"
- register "s0ix_enable" = "0"
+ # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x01220000"
- device domain 0 on
- device pci 13.0 on end # Smart Sound Audio DSP
- device pci 1b.0 off end # High Definition Audio
- device pci 1c.0 off end # PCIe Port #1
- device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
- device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
- device pci 1f.3 on end # SMBus
+ device pci 13.0 on end # Smart Sound Audio DSP
+ device pci 1b.0 off end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
+ device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
+ device pci 1f.3 on end # SMBus
+# end
end
end
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index 75c202d663..eae7999ea2 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
-
- device domain 0 on end
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+# end
+ end
end
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index 60aef30a58..dc70085dd0 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
-
- device domain 0 on end
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+# end
+ end
end
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index c5d27476c7..710fa95cac 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -10,30 +10,32 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- register "sata_port0_gen3_tx" = "0x72"
-
- # Set I2C0 to 1.8V
- register "sio_i2c0_voltage" = "1"
-
- # Force enable ASPM for PCIe Port 3
- register "pcie_port_force_aspm" = "0x04"
- register "pcie_port_coalesce" = "1"
-
- # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013b0000"
+ register "vr_slow_ramp_rate_set" = "3"
+ register "vr_slow_ramp_rate_enable" = "1"
# Disable S0ix for now
register "s0ix_enable" = "0"
- register "vr_slow_ramp_rate_set" = "3"
- register "vr_slow_ramp_rate_enable" = "1"
-
device domain 0 on
- device pci 13.0 on end # Smart Sound Audio DSP
- device pci 15.3 on end # GSPI0
- device pci 1b.0 off end # High Definition Audio
- device pci 1c.0 off end # PCIe Port #1
- device pci 1c.2 on end # PCIe Port #3
- device pci 1d.0 off end # USB2 EHCI
+# chip soc/intel/broadwell/pch
+ register "sata_port0_gen3_tx" = "0x72"
+
+ # Set I2C0 to 1.8V
+ register "sio_i2c0_voltage" = "1"
+
+ # Force enable ASPM for PCIe Port 3
+ register "pcie_port_force_aspm" = "0x04"
+ register "pcie_port_coalesce" = "1"
+
+ # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013b0000"
+
+ device pci 13.0 on end # Smart Sound Audio DSP
+ device pci 15.3 on end # GSPI0
+ device pci 1b.0 off end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1d.0 off end # USB2 EHCI
+# end
end
end