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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 22:54:22 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-11 18:42:07 +0100
commit9b9915284f5070c6f664fa36495ae831e95ea819 (patch)
tree3b078aeab72924c2a0981d0c06adc17d8afe3573
parent5ecc41b0c9226486da71d6aa95a505877f0fdaeb (diff)
downloadcoreboot-9b9915284f5070c6f664fa36495ae831e95ea819.tar.xz
intel/sandybridge: Use common ACPI S3 recovery
Fix regression, S3 resume not working on sandy/ivy after commit 9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes this delay by removing need of this backup entirely. Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15248 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc23
-rw-r--r--src/northbridge/intel/sandybridge/early_init.c10
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h6
3 files changed, 2 insertions, 37 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 6702155494..cc52637076 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -17,8 +17,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#include <arch/acpi.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
* and the space used by the reference code. These 2 values combined should
@@ -284,27 +282,6 @@ before_romstage:
post_code(0x3c)
-#if CONFIG_HAVE_ACPI_RESUME
- movl CBMEM_BOOT_MODE, %eax
- cmpl $0x2, %eax // Resume?
- jne __acpi_resume_backup_done
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high
- * tables memory completely, but that's a wonderful clean up task for
- * another day.
- */
- cld
- movl $CONFIG_RAMBASE, %esi
- movl CBMEM_RESUME_BACKUP, %edi
- movl $HIGH_MEMORY_SAVE >> 2, %ecx
- rep movsl
-
-__acpi_resume_backup_done:
-#endif
-
- post_code(0x3d)
-
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 779f29befd..a013ec3707 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -233,15 +233,9 @@ void northbridge_romstage_finalize(int s3resume)
* this is not a resume. In that case we just create the cbmem toc.
*/
- *(u32 *)CBMEM_BOOT_MODE = 0;
- *(u32 *)CBMEM_RESUME_BACKUP = 0;
-
if (s3resume) {
- void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
- if (resume_backup_memory) {
- *(u32 *)CBMEM_BOOT_MODE = 2;
- *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
- }
+ acpi_prepare_for_resume();
+
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
} else {
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 972ed9f0a2..e737e50f65 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -196,12 +196,6 @@
#define DMIDRCCFG 0xeb4 /* 32bit */
-/* Delegation of resume backup memory so we don't have to
- * (slowly) handle backing up OS memory in romstage.c
- */
-#define CBMEM_BOOT_MODE 0x610
-#define CBMEM_RESUME_BACKUP 0x614
-
#ifndef __ASSEMBLER__
static inline void barrier(void) { asm("" ::: "memory"); }