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authorAaron Durbin <adurbin@chromium.org>2016-07-25 11:30:43 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-27 00:39:48 +0200
commit9cbc90a1f6e197258ed47bc44016640f2b1e5a31 (patch)
tree4dae3a1bcd64ab1ca8c5bbb46811140423eb9975
parentaa3e8a8124fe82aa13eb828b0da69966e4d03cd1 (diff)
downloadcoreboot-9cbc90a1f6e197258ed47bc44016640f2b1e5a31.tar.xz
soc/nvidia/tegra124: remove cache_policiy option
All mainboards (nyans) utilizing the cache_policy option has it set to DCACHE_WRITETHROUGH. This option is for setting the framebuffer's cache attribute. However, this option is reliant on an architecture-specific enumeration. Just remove the option and use DCACHE_WRITETHROUGH across the board. If someone wants to reconfigure it at a later date one can introduce a non-architecture specific option. Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/mainboard/google/nyan/devicetree.cb2
-rw-r--r--src/mainboard/google/nyan_big/devicetree.cb2
-rw-r--r--src/mainboard/google/nyan_blaze/devicetree.cb2
-rw-r--r--src/soc/nvidia/tegra124/chip.h1
-rw-r--r--src/soc/nvidia/tegra124/display.c2
5 files changed, 1 insertions, 8 deletions
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index 1031b029fe..5db8192ac9 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -32,8 +32,6 @@ chip soc/nvidia/tegra124
register "panel_bits_per_pixel" = "18"
- register "cache_policy" = "DCACHE_WRITETHROUGH"
-
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb
index 1031b029fe..5db8192ac9 100644
--- a/src/mainboard/google/nyan_big/devicetree.cb
+++ b/src/mainboard/google/nyan_big/devicetree.cb
@@ -32,8 +32,6 @@ chip soc/nvidia/tegra124
register "panel_bits_per_pixel" = "18"
- register "cache_policy" = "DCACHE_WRITETHROUGH"
-
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"
diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb
index 1031b029fe..5db8192ac9 100644
--- a/src/mainboard/google/nyan_blaze/devicetree.cb
+++ b/src/mainboard/google/nyan_blaze/devicetree.cb
@@ -32,8 +32,6 @@ chip soc/nvidia/tegra124
register "panel_bits_per_pixel" = "18"
- register "cache_policy" = "DCACHE_WRITETHROUGH"
-
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"
diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h
index 186657f02f..6994ca2210 100644
--- a/src/soc/nvidia/tegra124/chip.h
+++ b/src/soc/nvidia/tegra124/chip.h
@@ -32,7 +32,6 @@ struct soc_nvidia_tegra124_config {
u32 framebuffer_bits_per_pixel;
u32 color_depth;
u32 panel_bits_per_pixel;
- int cache_policy;
/* there are two. It's not unimaginable that we might someday
* have two of these structs in a single mainboard.
*/
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index 9ec34d481f..dce6ad257a 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -263,7 +263,7 @@ void display_startup(device_t dev)
config->framebuffer_base = framebuffer_base_mb * MiB;
mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
- config->cache_policy);
+ DCACHE_WRITETHROUGH);
printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb,
framebuffer_base_mb + framebuffer_size_mb);