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| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-10-10 14:03:36 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-22 01:58:22 +0000 |
| commit | 9e0d69bf1e0194509108eba23511a12d597ae49e (patch) | |
| tree | 029971bc062e57fb1735fda490942fc9da22310e | |
| parent | c25c9988880bf7a3343419f0bc9cf782d8932c26 (diff) | |
| download | coreboot-9e0d69bf1e0194509108eba23511a12d597ae49e.tar.xz | |
soc/intel/skylake: pass SataSpeedLimit param to FSP2
The Librem13v2 needs to set this parameter to work around
power-related issues with some SATA devices.
Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22045
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 022306cef3..2c282bc17f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -148,6 +148,7 @@ struct soc_intel_skylake_config { u8 SataSalpSupport; u8 SataPortsEnable[8]; u8 SataPortsDevSlp[8]; + u8 SataSpeedLimit; /* Audio related */ u8 EnableAzalia; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f9bdf8a1ef..bc0f5a5678 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -206,6 +206,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Device4Enable = config->Device4Enable; params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; + params->SataSpeedLimit = config->SataSpeedLimit; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; /* |