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authorAngel Pons <th3fanbus@gmail.com>2020-10-25 13:49:09 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-04 22:58:25 +0000
commit9f8e92bae32129883bc1e16ef40915963bf4b17b (patch)
treef9eb3f33ce2005fc4d8b213bd9d6a0351a64ffa7
parent34c0b26193ea9424a7eaba4d0a4ab2d5925c2f91 (diff)
downloadcoreboot-9f8e92bae32129883bc1e16ef40915963bf4b17b.tar.xz
sb/intel/lynxpoint: Expose full LPC device ID in ACPI
This is merely to align ACPI files with Broadwell. It is unused. Change-Id: I8aa297bd3c3734bbd438ff84742aadfc661adcf7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46764 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/lpc.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index bc1d73cddf..0e8bad3f72 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -9,8 +9,8 @@ Device (LPCB)
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
Field (LPC0, AnyAcc, NoLock, Preserve)
{
- Offset (0x3),
- DIDH, 8, // Device ID High Byte
+ Offset (0x02),
+ PDID, 16, // Device ID
Offset (0x40),
PMBS, 16, // PMBASE
Offset (0x48),