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authorLijian Zhao <lijian.zhao@intel.com>2017-10-04 23:08:55 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-06 15:25:45 +0000
commita06f55b8e4a4e51815d654f6125a60c0db3550e4 (patch)
tree1722c4aefc423df1e02f11ffc476c139cea3f078
parent4a8f45f9ad541124688142b186d10b15b9867574 (diff)
downloadcoreboot-a06f55b8e4a4e51815d654f6125a60c0db3550e4.tar.xz
soc/intel/cannonlake: Enable MRC cache
Enable MRC cache by default. TEST=Warm reset and check coreboot serial log, MRC related log can be seen. Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/cannonlake/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 9153b04985..b60d3d54a6 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select C_ENVIRONMENT_BOOTBLOCK
+ select CACHE_MRC_SETTINGS
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
@@ -26,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select IOAPIC
+ select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0