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authorHuayang Duan <huayang.duan@mediatek.com>2020-06-22 19:36:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-08-26 07:35:59 +0000
commita0ef67879802f47c4e6e979fa0dd5a872960efc0 (patch)
treef5831fc0c6e3e2f43f18cfdc26e64e862d8a7db1
parent3c16fe4fade9f1c695a52e756fa638cb8cd0e9f6 (diff)
downloadcoreboot-a0ef67879802f47c4e6e979fa0dd5a872960efc0.tar.xz
mb/google/asurada: Load dram params from sdram config
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I2cc38115c27cbbe157fc850bbd88b10ae8001f52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
-rw-r--r--src/mainboard/google/asurada/Makefile.inc3
-rw-r--r--src/mainboard/google/asurada/sdram_configs.c25
-rw-r--r--src/mainboard/google/asurada/sdram_params/Makefile.inc10
-rw-r--r--src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c7
-rw-r--r--src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c7
5 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc
index 3f5968a98c..8395e4a35b 100644
--- a/src/mainboard/google/asurada/Makefile.inc
+++ b/src/mainboard/google/asurada/Makefile.inc
@@ -1,3 +1,5 @@
+subdirs-y += sdram_params/
+
bootblock-y += memlayout.ld
bootblock-y += bootblock.c
@@ -6,6 +8,7 @@ verstage-y += reset.c
romstage-y += memlayout.ld
romstage-y += boardid.c
+romstage-y += sdram_configs.c
ramstage-y += memlayout.ld
ramstage-y += boardid.c
diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c
new file mode 100644
index 0000000000..9efcb32dae
--- /dev/null
+++ b/src/mainboard/google/asurada/sdram_configs.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/dramc_param.h>
+
+static const char *const sdram_configs[] = {
+ [0] = "sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB",
+ [1] = "sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB",
+};
+
+static struct sdram_info params;
+
+const struct sdram_info *get_sdram_config(void)
+{
+ uint32_t ramcode = ram_code();
+
+ if (ramcode >= ARRAY_SIZE(sdram_configs) ||
+ cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params),
+ CBFS_TYPE_STRUCT) != sizeof(params))
+ die("Cannot load SDRAM parameter file for RAM code: %#x", ramcode);
+
+ return &params;
+}
diff --git a/src/mainboard/google/asurada/sdram_params/Makefile.inc b/src/mainboard/google/asurada/sdram_params/Makefile.inc
new file mode 100644
index 0000000000..acc8b5822f
--- /dev/null
+++ b/src/mainboard/google/asurada/sdram_params/Makefile.inc
@@ -0,0 +1,10 @@
+sdram-params :=
+sdram-params += sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB
+sdram-params += sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB
+
+$(foreach params,$(sdram-params), \
+ $(eval cbfs-files-y += $(params)) \
+ $(eval $(params)-file := $(params).c:struct) \
+ $(eval $(params)-type := struct) \
+ $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \
+)
diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c
new file mode 100644
index 0000000000..8ae9b69bb1
--- /dev/null
+++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+struct sdram_info params = {
+ .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0,
+};
diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c
new file mode 100644
index 0000000000..36fc0a29ce
--- /dev/null
+++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+struct sdram_info params = {
+ .ddr_geometry = DDR_TYPE_2CH_2RK_6GB_3_3,
+};