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authorJean Lucas <jean@4ray.co>2017-12-09 04:34:57 -0500
committerMartin Roth <martinroth@google.com>2018-01-07 18:46:24 +0000
commita241d6c76bf43b16a3022ae036e5b84822269ec7 (patch)
tree05cee10ce23f39211e0eccc9bd6fcc9ab75bda10
parent780a1c44e190427522ee27e887b2a9ab692eb594 (diff)
downloadcoreboot-a241d6c76bf43b16a3022ae036e5b84822269ec7.tar.xz
autoport: Add Intel PCIe Root Port and Bridges
- 0x0151: Xeon E3-1200 PCIe Root Port - 0x1e25: 7/C216 Series Chipset Family DMI to PCI Bridge - 0x2448: 82801 Mobile PCI Bridge - 0x244e: 82801 Desktop PCI Bridge Change-Id: I4111b73adc0f08d643c940cd43ab7fd4c0af7668 Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/22794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-rw-r--r--util/autoport/bd82x6x.go9
1 files changed, 5 insertions, 4 deletions
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index ce06a8167b..dc5d6897f4 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -439,10 +439,11 @@ func init() {
/* PCIe bridge */
for _, id := range []uint16{
- 0x1c10, 0x1c12, 0x1c14, 0x1c16,
- 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
- 0x1e10, 0x1e12, 0x1e14, 0x1e16,
- 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
+ 0x0151, 0x1c10, 0x1c12, 0x1c14,
+ 0x1c16, 0x1c18, 0x1c1a, 0x1c1c,
+ 0x1c1e, 0x1e10, 0x1e12, 0x1e14,
+ 0x1e16, 0x1e18, 0x1e1a, 0x1e1c,
+ 0x1e1e, 0x1e25, 0x244e, 0x2448,
} {
RegisterPCI(0x8086, id, GenericPCI{})
}