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authorBernardo Perez Priego <bernardo.perez.priego@intel.com>2019-10-03 18:20:37 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-10-09 22:17:36 +0000
commita31e6e84974006188baa394027eebd78a9da550c (patch)
tree91da724b0849bd0f2e9d47790c7224c1f5e7e3d6
parent2ef5d1af867678318cac28bb948f152de9c01c49 (diff)
downloadcoreboot-a31e6e84974006188baa394027eebd78a9da550c.tar.xz
mb/google/drallion: Enable UART console for arcada_cml and sarien_cml
Drallion uses UART 0 for console, other two variants remain as UART 2. BUG=b:139095062 TEST=emerge-drallion coreboot chromeos-bootimage. Console should be visible. Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35785 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/drallion/Kconfig4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index 35f7150836..256f8cbdae 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -84,7 +84,9 @@ config MAX_CPUS
config UART_FOR_CONSOLE
int
- default 0
+ default 2 if BOARD_GOOGLE_ARCADA_CML
+ default 2 if BOARD_GOOGLE_SARIEN_CML
+ default 0 if BOARD_GOOGLE_DRALLION
config VARIANT_DIR
string