summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-08-21 14:21:03 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-09-09 13:27:06 +0000
commita546f11c6d5ad8970bd6022a52b1f2e6c5abab4b (patch)
treee52dfe036d8a995f7c1368deadc24098d8624619
parent033435b75f339eaea82c0710bd99f2da586d3e29 (diff)
downloadcoreboot-a546f11c6d5ad8970bd6022a52b1f2e6c5abab4b.tar.xz
mb/asrock/h110m: fix VR domains configuration
1) VR domains current limit Icc max for Sky/Kaby Lake S is set based on the processor TDP [1]. Updates information about this 2) Sets VR voltage limit to 1.52V, as described in the datasheets [2,3] [1] Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde [2] page 112-119, 6th Generation Intel(R) Processor Families for S-Platforms, Volume 1 of 2, Datasheet, August 2018. Document Number: 332687-008EN [3] 7th Generation Intel(R) Processor Families for S Platforms and Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1, December 2018, Document Number: 335195-003 Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 3067ffe53c..53705684b2 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -89,9 +89,10 @@ chip soc/intel/skylake
#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| IccMax* | 0 | 0 | 0 | 0 | 0 |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------------+-------------+-------+
+ # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = 0x50, \
@@ -102,7 +103,7 @@ chip soc/intel/skylake
.imon_slope = 0x0, \
.imon_offset = 0x0, \
.icc_max = 0x0, \
- .voltage_limit = 0x0 \
+ .voltage_limit = 1520 \
}"
register "domain_vr_config[VR_IA_CORE]" = "{
@@ -115,7 +116,7 @@ chip soc/intel/skylake
.imon_slope = 0x0, \
.imon_offset = 0x0, \
.icc_max = 0x0, \
- .voltage_limit = 0x0 \
+ .voltage_limit = 1520 \
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -128,7 +129,7 @@ chip soc/intel/skylake
.imon_slope = 0x0, \
.imon_offset = 0x0, \
.icc_max = 0x0 ,\
- .voltage_limit = 0x0 \
+ .voltage_limit = 1520 \
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -141,7 +142,7 @@ chip soc/intel/skylake
.imon_slope = 0x0, \
.imon_offset = 0x0, \
.icc_max = 0x0, \
- .voltage_limit = 0x0 \
+ .voltage_limit = 1520 \
}"
register "EnableLan" = "0"