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authorFurquan Shaikh <furquan@google.com>2019-12-11 10:15:59 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-12 15:09:09 +0000
commita6eab80dc9128e8ab82e997159c72906f989ee6c (patch)
treed22088c048687db4fb44a9690f85d81745019eed
parent149d523c9a52446bbcf38fa0b5afc9b0c722efb9 (diff)
downloadcoreboot-a6eab80dc9128e8ab82e997159c72906f989ee6c.tar.xz
soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h
gpe0_en_* seem to have been copied over from previous generations but recent SoCs don't use it. This change gets rid of these unused members. Change-Id: I165e66aeefde4efea4484f588c774795987ca461 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/soc/intel/cannonlake/chip.h6
-rw-r--r--src/soc/intel/icelake/chip.h6
-rw-r--r--src/soc/intel/skylake/chip.h5
-rw-r--r--src/soc/intel/tigerlake/chip.h6
4 files changed, 0 insertions, 23 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index f08fd0a95e..85c33db07b 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -45,12 +45,6 @@ struct soc_intel_cannonlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
- /* GPE configuration */
- uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
- uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
- uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
- uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
-
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form GPP_[A:G] or GPD. */
uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index ec625a0049..068751324f 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -35,12 +35,6 @@ struct soc_intel_icelake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
- /* GPE configuration */
- uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
- uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
- uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
- uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
-
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form GPP_[A:G] or GPD. */
uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 636266632e..b189a16a05 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -73,11 +73,6 @@ struct soc_intel_skylake_config {
uint8_t pirqg_routing;
uint8_t pirqh_routing;
- /* GPE configuration */
- uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
- uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
- uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
- uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form GPP_[A:G] or GPD. */
uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 32dc02c666..5e0fcd11c5 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -35,12 +35,6 @@ struct soc_intel_tigerlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
- /* GPE configuration */
- uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
- uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
- uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
- uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
-
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form GPP_[A:G] or GPD. */
uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */