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authorRonald G. Minnich <rminnich@gmail.com>2006-08-08 18:02:12 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-08-08 18:02:12 +0000
commita758acab7fe1561b4b40098efeb66f6da6db01c9 (patch)
tree996b9fdb414aa63b8d121dd75055bae20ed3dc3d
parent90e68aef683a89c0560cd56fd18baba2570b4512 (diff)
downloadcoreboot-a758acab7fe1561b4b40098efeb66f6da6db01c9.tar.xz
fix up config space.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/sunw/ultra40/resourcemap.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c
index ea572a5d29..08a0443ebe 100644
--- a/src/mainboard/sunw/ultra40/resourcemap.c
+++ b/src/mainboard/sunw/ultra40/resourcemap.c
@@ -3,7 +3,7 @@
*
*/
-static void setup_s2895_resource_map(void)
+static void setup_ultra40_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
@@ -253,11 +253,10 @@ static void setup_s2895_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
+ PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
+ PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
+ PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
};
int max;