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authorPatrick Rudolph <siro@das-labor.org>2018-01-29 11:59:01 +0100
committerMartin Roth <martinroth@google.com>2018-01-31 15:23:56 +0000
commita88697444aa9fd4dbf228fe01f8689969a7ec2ce (patch)
tree0fb2ef94648f18fd1b38ec8b2d68b8662280040c
parent662b6cb3ed5f4f11231d9675cadcd47798399074 (diff)
downloadcoreboot-a88697444aa9fd4dbf228fe01f8689969a7ec2ce.tar.xz
nb/intel/*.h: Remove left-over register definitions
The code has been moved into drivers folder. Change-Id: I122affffd5108052ed7a95b34d0d66a6d3279d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/northbridge/intel/fsp_sandybridge/northbridge.h2
-rw-r--r--src/northbridge/intel/haswell/haswell.h2
-rw-r--r--src/northbridge/intel/nehalem/nehalem.h2
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h2
4 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index c0194f20a8..233cca79cc 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -109,8 +109,6 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
-#define SWSCI 0xe8 /* SWSCI enable */
-#define ASLS 0xfc /* OpRegion Base */
/*
* MCHBAR
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 2d03a68da1..b7954e8499 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -96,8 +96,6 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
-#define SWSCI 0xe8 /* SWSCI enable */
-#define ASLS 0xfc /* OpRegion Base */
/*
* MCHBAR
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index a693e12f01..7a460fc054 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -195,8 +195,6 @@ typedef struct {
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
-#define SWSCI 0xe8 /* SWSCI enable */
-#define ASLS 0xfc /* OpRegion Base */
/*
* MCHBAR
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 1f56585315..8bbfae92a0 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -114,8 +114,6 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
-#define SWSCI 0xe8 /* SWSCI enable */
-#define ASLS 0xfc /* OpRegion Base */
/*
* MCHBAR