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authorhenryc.chen <henryc.chen@mediatek.com>2016-03-07 15:17:01 +0800
committerMartin Roth <martinroth@google.com>2016-03-18 18:56:23 +0100
commitaad2903c9ceefa9ffb86660c07a7b3eb1ead46b5 (patch)
treea171e5c8de96ee84becfa613b72a4cd4c3dc4830
parent32154d7b1211faab3d37eab0b00154a7f190eb23 (diff)
downloadcoreboot-aad2903c9ceefa9ffb86660c07a7b3eb1ead46b5.tar.xz
mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN
When system enters suspend, SPM will pull SRCVOLTEN low to turn off some power rails. VSRMCA7 should follow this pin to turn on/off the power. BRANCH=none BUG=none TEST=verified on Oak rev5 Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332345 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/mediatek/mt8173/mt6391.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index 9f5ed0a253..ced86d7ff0 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -299,7 +299,7 @@ static void mt6391_init_setting(void)
/* [6:0]: VSRMCA7_VOSEL_SLEEP; */
mt6391_write(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0);
/* [8:8]: VSRMCA7_VSLEEP_EN; */
- mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x1, 0x1, 8);
+ mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8);
/* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */
mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4);
/* [8:8]: VDRM_VSLEEP_EN; */
@@ -362,6 +362,8 @@ static void mt6391_init_setting(void)
mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1);
/* [1:1]: VSRMCA7_VOSEL_CTRL; */
mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1);
+ /* [0:0]: VSRMCA7_EN_CTRL; */
+ mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0);
/* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */
mt6391_write(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4);
/* [4:4]: VSRMCA15_TRACK_ON_CTRL; */