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authorZheng Bao <fishbaozi@gmail.com>2021-01-19 22:37:59 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-01-27 15:43:55 +0000
commitb04405ff766db9b4d0d6665b28d4860788fb6889 (patch)
tree306ffb9fded3a8157a724921e11603d4db4f9c3a
parent20f5687def94c96d60e92cd990d595b0efd8161b (diff)
downloadcoreboot-b04405ff766db9b4d0d6665b28d4860788fb6889.tar.xz
soc/amd/cezanne: Add UCODE firmware to CBFS
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-rw-r--r--src/soc/amd/cezanne/Kconfig1
-rw-r--r--src/soc/amd/cezanne/Makefile.inc4
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 9b766736f0..c34f127393 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -31,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS
select SSE2
select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS
+ select SUPPORT_CPU_UCODE_IN_CBFS
config CHIPSET_DEVICETREE
string
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index ef099de593..bcf1d722c4 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -101,8 +101,6 @@ PSP_ELF_FILE=$(objcbfs)/bootblock.elf
PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
-# type = 0x66
-
# type = 0xb - See #55758 (NDA) for bit definitions.
PSP_SOFTFUSE_BITS += 28
@@ -183,4 +181,6 @@ apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(CEZANNE_FWM_POSITION)
apu/amdfw-type := raw
+cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin)
+
endif # ($(CONFIG_SOC_AMD_CEZANNE),y)