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authorNaresh G Solanki <naresh.solanki@intel.com>2018-04-02 21:49:51 +0530
committerAaron Durbin <adurbin@chromium.org>2018-04-09 17:05:59 +0000
commitb10e96f1969bf7ab1a4c83abc484aa4873af950e (patch)
treefd2559bf582cfdc307ce33e03eb715bafe5bbc89
parent68a1542692f5674704ece3c4716924f30947a2a3 (diff)
downloadcoreboot-b10e96f1969bf7ab1a4c83abc484aa4873af950e.tar.xz
soc/intel/common: Add funtion to modify PAT & NXE bit
Add function to modify NXE bit & PAT. BUG=None BRANCH=None TEST=Make sure build for Glkrvp is successful. Change-Id: I265d6d5ca538496934a375eb8d99d52879522051 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25480 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c20
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h5
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h10
3 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 0d6dacc628..ed1ba0fa7b 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -314,3 +314,23 @@ void mca_configure(void)
(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
}
}
+
+void set_nxe(uint8_t enable)
+{
+ msr_t msr = rdmsr(IA32_EFER);
+
+ if (enable)
+ msr.lo |= EFER_NXE;
+ else
+ msr.lo &= ~EFER_NXE;
+
+ wrmsr(IA32_EFER, msr);
+}
+
+void set_pat(uint64_t pat)
+{
+ msr_t msr;
+ msr.lo = pat;
+ msr.hi = pat >> 32;
+ wrmsr(MSR_IA32_PAT, msr);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 34caf4c252..0c7f2c42d3 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -159,4 +159,9 @@ uint32_t cpu_get_max_turbo_ratio(void);
/* Configure Machine Check Architecture support */
void mca_configure(void);
+/* Set/Clear NXE bit in IA32_EFER MSR */
+void set_nxe(uint8_t enable);
+
+/* Set PAT MSR */
+void set_pat(uint64_t pat);
#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 22e8862e98..5cfce17894 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -72,6 +72,7 @@
#define PRMRR_PHYS_MASK_LOCK (1 << 10)
#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_POWER_CTL 0x1fc
+#define MSR_IA32_PAT 0x277
#define MSR_EVICT_CTL 0x2e0
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
@@ -142,4 +143,13 @@
#define SGX_RESOURCE_MASK_LO (0xfffff000UL)
#define SGX_RESOURCE_MASK_HI (0xfffffUL)
+/* Intel SDM: Table 2-1
+ * IA-32 architectural MSR: Extended Feature Enable Register
+ */
+#define IA32_EFER 0xC0000080
+#define EFER_NXE (1 << 11)
+#define EFER_LMA (1 << 10)
+#define EFER_LME (1 << 8)
+#define EFER_SCE (1 << 0)
+
#endif /* SOC_INTEL_COMMON_MSR_H */