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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-30 13:48:24 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-31 23:09:29 +0200
commitb3ddf83a118a7b1ae374ec00cd98420331f36cb1 (patch)
tree0a55098f1b2eb454256ba113612af8dfdaad8690
parente35db2c6eb66945d443f60ad2ba6e0e0fed27ad1 (diff)
downloadcoreboot-b3ddf83a118a7b1ae374ec00cd98420331f36cb1.tar.xz
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14192 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/northbridge/amd/amdfam10/misc_control.c46
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.h1
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c10
4 files changed, 49 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index d6f9fd9437..de9f34233f 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -30,6 +30,7 @@
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <lib.h>
+#include <cbmem.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "amdfam10.h"
@@ -152,6 +153,51 @@ static void misc_control_init(struct device *dev)
printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
+#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA)
+ uint8_t node;
+ uint8_t slot;
+ uint8_t dimm_present;
+
+ /* Restore DRAM MCA registers */
+ struct amdmct_memory_info *mem_info;
+ mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO);
+ if (mem_info) {
+ node = PCI_SLOT(dev->path.pci.devfn) - 0x18;
+
+ /* Check node for installed DIMMs */
+ dimm_present = 0;
+
+ /* Check all slots for installed DIMMs */
+ for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) {
+ if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) {
+ dimm_present = 1;
+ break;
+ }
+ }
+
+ if (dimm_present) {
+ uint32_t mc4_status_high = pci_read_config32(dev, 0x4c);
+ uint32_t mc4_status_low = pci_read_config32(dev, 0x48);
+ if (mc4_status_high != 0) {
+ printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n"
+ "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low);
+ }
+
+ /* Clear MC4 error status */
+ pci_write_config32(dev, 0x48, 0x0);
+ pci_write_config32(dev, 0x4c, 0x0);
+
+ if (mem_info->dct_stat[node].mca_config_backed_up) {
+ dword = pci_read_config32(dev, 0x44);
+ dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30;
+ dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21;
+ dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
+ pci_write_config32(dev, 0x44, dword);
+ }
+ }
+ }
+#endif
+
/* Disable Machine checks from Invalid Locations.
* This is needed for PC backwards compatibility.
*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 2de7521d7a..0b8833124e 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -8024,8 +8024,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1;
pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1;
+ pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1;
dword &= ~(0x1 << 30);
dword &= ~(0x1 << 21);
+ dword &= ~(0x1 << 2);
Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
pDCTstat->mca_config_backed_up = 1;
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index 6031239c06..67eb2b4869 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -584,6 +584,7 @@ struct DCTStatStruc { /* A per Node structure*/
uint8_t mca_config_backed_up;
uint8_t sync_flood_on_dram_err;
uint8_t sync_flood_on_any_uc_err;
+ uint8_t sync_flood_on_uc_dram_ecc_err;
/* New for LB Support */
u8 NodePresent;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 07eb0bd269..1077cb8f89 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
u32 val;
u16 nvbits;
- uint32_t dword;
-
mctHookBeforeECC();
/* Construct these booleans, based on setup options, for easy handling
@@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
/* Clear MC4 error status */
pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
-
- /* Restore previous MCA error handling settings */
- if (pDCTstat->mca_config_backed_up) {
- dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
- dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
- dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
- Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
- }
}
}
}