diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-01 21:36:32 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-05 09:19:28 +0000 |
| commit | b70c66b00d5741d3ba4eac96d75defab0dbec434 (patch) | |
| tree | 7b0ab585504d82dd88e76e5ad01ea24d49327fa5 | |
| parent | 11ca2ae167f4dbcfdb9a98d53232e19a31b4977b (diff) | |
| download | coreboot-b70c66b00d5741d3ba4eac96d75defab0dbec434.tar.xz | |
nb/intel/ironlake: Drop unnecessary `smm_region_start` function
Change-Id: I4c4b40b2b4f54b7756b8485dad80a1b4786270f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/northbridge/intel/ironlake/memmap.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 54337ccd69..78fbae85fe 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -11,16 +11,10 @@ #include "ironlake.h" -static uintptr_t smm_region_start(void) -{ - /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return tom; -} - static uintptr_t northbridge_get_tseg_base(void) { - return smm_region_start(); + /* Base of TSEG is top of usable DRAM */ + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); } static size_t northbridge_get_tseg_size(void) @@ -30,7 +24,7 @@ static size_t northbridge_get_tseg_size(void) void *cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return (void *)northbridge_get_tseg_base(); } void smm_region(uintptr_t *start, size_t *size) |