diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-09-20 17:32:20 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 09:02:45 +0000 |
| commit | b878c19810f48633461271c8bf5ed97960950c96 (patch) | |
| tree | 63bab204ecbc42cc96f38bca3f5d3b0d247737f6 | |
| parent | e911158d3e3899e27f332149caa14f6e902d184b (diff) | |
| download | coreboot-b878c19810f48633461271c8bf5ed97960950c96.tar.xz | |
mb/google/dragonegg: Enable audio
BUG=b:116191230
BRANCH=None
TEST=1. verified boot beep support at depthcharge.
Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29753
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb | 34 | ||||
| -rw-r--r-- | src/mainboard/google/dragonegg/variants/baseboard/gpio.c | 8 |
2 files changed, 40 insertions, 2 deletions
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index eff9107cc7..257ad1dd15 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -12,6 +12,10 @@ chip soc/intel/icelake device lapic 0 on end end + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkSsp0" = "1" + register "PchHdaAudioLinkSsp1" = "1" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" @@ -152,6 +156,15 @@ chip soc/intel/icelake .speed_mhz = 1, .early_init = 1, }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, }" device domain 0 on @@ -237,7 +250,24 @@ chip soc/intel/icelake end end # I2C #1 device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 on + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -281,7 +311,7 @@ chip soc/intel/icelake device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c index 5930514f8d..56f62193bd 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c @@ -49,12 +49,20 @@ static const struct pad_config gpio_table[] = { /* USB_C0_SBU_2_DC */ PAD_CFG_GPO(GPP_E23, 0, DEEP), /* CNV_RF_RESET_N */ PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1), /* CNV_CLKREQ0 */ PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2), +/* SPKR_IRQ_L */ PAD_CFG_GPI_APIC(GPP_F6, NONE, DEEP, LEVEL, NONE), +/* SPKR_RST_L */ PAD_CFG_GPO(GPP_F19, 1, DEEP), /* SD_CD# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP), /* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST), /* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST), /* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST), /* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST), +/* I2S0_SCLK */ PAD_CFG_GPO(GPP_R0, 1, DEEP), +/* I2S0_SFRM */ PAD_CFG_GPO(GPP_R1, 1, DEEP), +/* I2S0_TXD */ PAD_CFG_GPO(GPP_R2, 1, DEEP), +/* I2S0_RXD */ PAD_CFG_GPI(GPP_R3, NONE, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { |