diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 15:11:55 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 12:22:40 +0000 |
| commit | b9bbed2c41a64b60013080494d0125415fbcfdca (patch) | |
| tree | 5299d8e938f3c14904044dbe581ad61e5b532f11 | |
| parent | b053583a1c372a0b7018241a5e6bd2d8d00b843c (diff) | |
| download | coreboot-b9bbed2c41a64b60013080494d0125415fbcfdca.tar.xz | |
nb/intel/gm45/northbridge.c: Use `MiB` definition
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ibfa9a6fa7818d0bd79d2c0d9331c0ca38a2b7fe3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 0308e216c7..e58ed0d967 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -37,15 +38,15 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ *base = pciexbar_reg & (0x0f << 28); - *len = 256 * 1024 * 1024; + *len = 256 * MiB; return 1; case 1: /* 128M */ *base = pciexbar_reg & (0x1f << 27); - *len = 128 * 1024 * 1024; + *len = 128 * MiB; return 1; case 2: /* 64M */ *base = pciexbar_reg & (0x3f << 26); - *len = 64 * 1024 * 1024; + *len = 64 * MiB; return 1; } |