diff options
| author | Duncan Laurie <dlaurie@google.com> | 2020-11-17 10:13:05 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-12-10 18:13:12 +0000 |
| commit | bd8bb8eae0bdf4dec2b92a8be50c5286e34d7e0f (patch) | |
| tree | 957ec77fdd1e483443451f6a82a5db27de298d99 | |
| parent | 7590c370d64ad5d088feee879c76a38a18621776 (diff) | |
| download | coreboot-bd8bb8eae0bdf4dec2b92a8be50c5286e34d7e0f.tar.xz | |
drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
Configure the CFG2 register to set the latency to <64us in order
to ensure the L1 exit latency is consistent across devices and that
L1 ASPM is always enabled.
This moves the setup code from device init to device enable so it
executes before coreboot does ASPM configuration, and removes the
call to pci_dev_init() as that is just for VGA Option ROMs.
BUG=b:173207454
TEST=Verify the device and link capability and control for L1:
DevCap: Latency L1 <64us
LnkCap: Latency L1 <64us
LnkCtl: ASPM L1 Enabled
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/drivers/genesyslogic/gl9755/gl9755.c | 17 | ||||
| -rw-r--r-- | src/drivers/genesyslogic/gl9755/gl9755.h | 8 |
2 files changed, 21 insertions, 4 deletions
diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c index c3cdef11e7..6dfac47293 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.c +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -10,15 +10,24 @@ #include <device/pci_ids.h> #include "gl9755.h" -static void gl9755_init(struct device *dev) +static void gl9755_enable(struct device *dev) { - printk(BIOS_INFO, "GL9755: init\n"); - pci_dev_init(dev); + uint32_t reg; + + printk(BIOS_INFO, "GL9755: configure ASPM and LTR\n"); /* Set Vendor Config to be configurable */ pci_or_config32(dev, CFG, CFG_EN); + /* Set LTR value */ pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE); + + /* Adjust L1 exit latency to enable ASPM */ + reg = pci_read_config32(dev, CFG2); + reg &= ~CFG2_LAT_L1_MASK; + reg |= CFG2_LAT_L1_64US; + pci_write_config32(dev, CFG2, reg); + /* Set Vendor Config to be non-configurable */ pci_and_config32(dev, CFG, ~CFG_EN); } @@ -28,7 +37,7 @@ static struct device_operations gl9755_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, - .init = gl9755_init, + .enable = gl9755_enable }; static const unsigned short pci_device_ids[] = { diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h index 2d20faf695..aa20a527f2 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.h +++ b/src/drivers/genesyslogic/gl9755/gl9755.h @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef DRIVERS_GENESYSLOGIC_GL9755_H +#define DRIVERS_GENESYSLOGIC_GL9755_H + /* Definitions for Genesys Logic GL9755 */ #define CFG 0x800 #define CFG_EN 0x1 +#define CFG2 0x48 +#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3)) +#define CFG2_LAT_L1_64US ((0x6 << 12) | (0x6 << 3)) #define LTR 0x5C #define SNOOP_VALUE 0x25 #define SNOOP_SCALE (0x3 << 10) #define NO_SNOOP_VALUE (0x25 << 16) #define NO_SNOOP_SCALE (0x3 << 26) + +#endif /* DRIVERS_GENESYSLOGIC_GL9755_H */ |