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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-16 01:12:00 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-22 20:02:58 +0000 |
| commit | c037695c195595d9ecc2112d0359b37cfe253345 (patch) | |
| tree | 48cda407cd5aa4eb89b069d9c629421c1bbb5bde | |
| parent | 8f7e2a3add50f53361704a0e16466dd4c91e2416 (diff) | |
| download | coreboot-c037695c195595d9ecc2112d0359b37cfe253345.tar.xz | |
sec/intel/txt/ramstage.c: Do not init the heap on S3 resume
It causes problems on Haswell: SINIT detects that the heap tables differ
in size, and then issues a Class Code 9, Major Error Code 1 TXT reset.
Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/security/intel/txt/ramstage.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 2d56d1fd61..00e9ce72a2 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -407,7 +407,9 @@ static void lockdown_intel_txt(void *unused) write64((void *)TXT_MSEG_SIZE, 0); write64((void *)TXT_MSEG_BASE, 0); - txt_initialize_heap(); + /* Only initialize the heap on regular boots */ + if (!acpi_is_wakeup_s3()) + txt_initialize_heap(); if (CONFIG(INTEL_TXT_LOGGING)) txt_dump_regions(); |