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authorPatrick Georgi <pgeorgi@chromium.org>2016-07-29 18:23:32 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 19:20:27 +0200
commitc09160436343ff7f7ce70015f4cca5a03b315f18 (patch)
treeaca0e83bd2d5b3188562b92a40c668026bcb5b95
parent21ce6efe289ecc8eb6f047ceb3c3c25303e7272e (diff)
downloadcoreboot-c09160436343ff7f7ce70015f4cca5a03b315f18.tar.xz
sis/sis966: fix typo
temp8 & (!0x10) == temp8 & 0 == 0, which is certainly not intended. Change-Id: Ie9f735d31eedbec171f82929a147fc1b2e30b45a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229587 Reviewed-on: https://review.coreboot.org/15961 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/southbridge/sis/sis966/early_smbus.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index df91c86905..15d4f4ceef 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -578,7 +578,7 @@ static void sis_init_stage1(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit
temp8 = pci_read_config8(dev, 0x4C);
GUI_En = temp8 & 0x10;
- pci_write_config8(dev, 0x4C, temp8 & (!0x10));
+ pci_write_config8(dev, 0x4C, temp8 & (~0x10));
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
i=0;