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authorSubrata Banik <subrata.banik@intel.com>2017-07-21 10:08:25 +0530
committerAaron Durbin <adurbin@chromium.org>2017-07-21 14:46:13 +0000
commitc3198543b690fbdeda0f1e1ffaf78048fe765ec0 (patch)
treee290487cbf5c37ec549d4baf5dc33a1141a48415
parent8e39009c57dc92e6970a812ec82a2cee4cb6ced5 (diff)
downloadcoreboot-c3198543b690fbdeda0f1e1ffaf78048fe765ec0.tar.xz
soc/intel/skylake: Perform LPC offset read after lockdown operation
This patch is to provide an additional read LPC pci offset register BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is successful. Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/skylake/finalize.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 171d92e9cd..34f26eb8cb 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -185,6 +185,9 @@ static void soc_lockdown(void)
pci_read_config8(PCH_DEV_LPC,
BIOS_CNTL) | LPC_BC_LE);
+ /* Ensure an additional read back after performing lock down */
+ pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+
fast_spi_set_lock_enable();
}
@@ -194,6 +197,9 @@ static void soc_lockdown(void)
pci_read_config8(PCH_DEV_LPC,
BIOS_CNTL) | LPC_BC_EISS);
+ /* Ensure an additional read back after performing lock down */
+ pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+
fast_spi_set_eiss();
}
}