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authorFrans Hendriks <fhendriks@eltan.com>2018-10-30 15:07:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-02-28 17:09:29 +0000
commitc6d672fe1dbfe9c07cea0c84aa2f512297e690ed (patch)
treef18004cebf160859ee693df8a0b302a84c23401e
parentfa011db6f0ede9073c993aff0be88ec2353cf926 (diff)
downloadcoreboot-c6d672fe1dbfe9c07cea0c84aa2f512297e690ed.tar.xz
src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area
Calculation of memory reserved by FSP is incorrect. Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area BUG=N/A TEST=Intel CherryHill CRB Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
-rw-r--r--src/soc/intel/braswell/northcluster.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 6e148b9b01..c54c2c8f3c 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -94,6 +94,7 @@ static void nc_read_resources(struct device *dev)
unsigned long fsp_res_base_k;
unsigned long base_k, size_k;
const unsigned long four_gig_kib = (4 << (30 - 10));
+ void *fsp_reserved_memory_area;
int index = 0;
/* Read standard PCI resources. */
@@ -105,7 +106,14 @@ static void nc_read_resources(struct device *dev)
tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);
/* Determine the base of the FSP reserved memory */
- fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top());
+ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
+ if (fsp_reserved_memory_area) {
+ fsp_res_base_k =
+ RES_IN_KIB((unsigned int)fsp_reserved_memory_area);
+ } else {
+ /* If no FSP reserverd area */
+ fsp_res_base_k = tseg_base_k;
+ }
/* PCIe memory-mapped config space access - 256 MiB. */
mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
@@ -116,8 +124,8 @@ static void nc_read_resources(struct device *dev)
size_k = RES_IN_KIB(0xa0000) - base_k;
ram_resource(dev, index++, base_k, size_k);
- /* 0xc0000 -> fsp_res_base - cacheable and usable */
- base_k = RES_IN_KIB(0xc0000);
+ /* High memory -> fsp_res_base - cacheable and usable */
+ base_k = RES_IN_KIB(0x100000);
size_k = fsp_res_base_k - base_k;
ram_resource(dev, index++, base_k, size_k);