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authorJason Schildt <jschildt@gmail.com>2005-10-25 21:04:09 +0000
committerJason Schildt <jschildt@gmail.com>2005-10-25 21:04:09 +0000
commitc9c4dd65ac5892530b70d93f586fe1de9f0bc1f7 (patch)
treea716b11dc618e90b09ccf088e4be9e621dcb9193
parent4b18e2048f717d0e274b557dbda0829e8d6d6451 (diff)
downloadcoreboot-c9c4dd65ac5892530b70d93f586fe1de9f0bc1f7.tar.xz
- Issue Tracker ID-2 "lnxi-patch-2".
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/southbridge/amd/amd8111/Config.lb9
-rw-r--r--src/southbridge/amd/amd8111/amd8111_lpc.c12
-rw-r--r--src/southbridge/amd/amd8111/amd8111_usb2.c29
3 files changed, 20 insertions, 30 deletions
diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb
index 9b53c26da4..a69229260b 100644
--- a/src/southbridge/amd/amd8111/Config.lb
+++ b/src/southbridge/amd/amd8111/Config.lb
@@ -1,12 +1,11 @@
config chip.h
driver amd8111.o
-#driver amd8111_usb.o
+driver amd8111_usb.o
driver amd8111_lpc.o
driver amd8111_ide.o
driver amd8111_acpi.o
-#driver amd8111_usb2.o
-#driver amd8111_ac97.o
-#driver amd8111_nic.o
+driver amd8111_usb2.o
+driver amd8111_ac97.o
+driver amd8111_nic.o
driver amd8111_pci.o
driver amd8111_smbus.o
-object amd8111_reset.o
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 65c1ccb013..49246d93d4 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -84,7 +84,7 @@ static void setup_ioapic(void)
return;
}
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
+ a->reg, a->value_low, a->value_high);
}
}
@@ -113,13 +113,9 @@ static void lpc_init(struct device *dev)
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
- /* power after power fail */
+ /* Enable 5Mib Rom window */
byte = pci_read_config8(dev, 0x43);
- if (pwr_on) {
- byte &= ~(1<<6);
- } else {
- byte |= (1<<6);
- }
+ byte |= 0xC0;
pci_write_config8(dev, 0x43, byte);
/* Enable Port 92 fast reset */
@@ -179,7 +175,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x70,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c
index 8ec9dc8abf..1bec894ac8 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb2.c
+++ b/src/southbridge/amd/amd8111/amd8111_usb2.c
@@ -7,21 +7,7 @@
#include <device/pci_ops.h>
#include "amd8111.h"
-static void usb2_init(struct device *dev)
-{
- uint32_t cmd;
-
#if 0
- printk_debug("USB: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-
-
- printk_debug("done.\n");
-#endif
-}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
@@ -33,14 +19,23 @@ static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
};
+#endif
+
+static void amd8111_usb2_enable(device_t dev)
+{
+ // Due to buggy USB2 we force it to disable.
+ dev->enable = 0;
+ amd8111_enable(dev);
+ printk_debug("USB2 disabled.\n");
+}
+
static struct device_operations usb2_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = usb2_init,
.scan_bus = 0,
- .enable = amd8111_enable,
- .ops_pci = &lops_pci,
+ .enable = amd8111_usb2_enable,
+ // .ops_pci = &lops_pci,
};
static struct pci_driver usb2_driver __pci_driver = {