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| author | Rudolf Marek <r.marek@assembler.cz> | 2013-05-01 22:29:13 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-05-04 00:26:36 +0200 |
| commit | cc76d7e011ead7350c8b7017c401a584e88154e2 (patch) | |
| tree | 4b9bae55b5a8952fdcff50cd1a7109c3e79e73d0 | |
| parent | dfb0686f8435d8e637a3ab23bc07b0ef5caef0e9 (diff) | |
| download | coreboot-cc76d7e011ead7350c8b7017c401a584e88154e2.tar.xz | |
Asus F2A85-M Enable the SD controller for F2A85-M
If the SD controller is "off" hudson.c won't disable that because,
there is no code for this yet.
The PCI device is still visible and PCI BAR will be allocated
by Linux. Unfortunately it may happen that the particular address
is used by non-standard BAR for SPI controller.
Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3167
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/asus/f2a85-m/devicetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 8272964b13..0014381a64 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -102,7 +102,8 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. device pci 14.5 on end # USB 2 device pci 14.6 off end # Gec - device pci 14.7 off end + # SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away) + device pci 14.7 on end device pci 15.0 on end # PCIe 0 - onboard PCIe 1x device pci 15.1 on end # PCIe 1 onboard gigabit device pci 15.2 off end # unused |