diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-02-15 08:31:48 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-18 20:24:27 +0000 |
| commit | cd7873a28a311847bdd1fd7f74d2a6d0f66ede62 (patch) | |
| tree | 89312ec1f412e9733fa87b206a2a3ec4dc35c542 | |
| parent | 2cb7de09b2a56b05a9c44846b62f70150c591043 (diff) | |
| download | coreboot-cd7873a28a311847bdd1fd7f74d2a6d0f66ede62.tar.xz | |
mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
| -rw-r--r-- | src/mainboard/google/sarien/chromeos.fmd | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 2408a30403..db0af0f0aa 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -8,8 +8,8 @@ FLASH@0xfe000000 0x2000000 { } SI_BIOS@0x400000 0x1c00000 { RW_DIAG@0x0 0x12d0000 { - DIAG_NVRAM@0x0 0x10000 - RW_LEGACY(CBFS)@0x10000 0x12c0000 + RW_LEGACY(CBFS)@0x0 0x12c0000 + DIAG_NVRAM@0x12c0000 0x10000 } RW_SECTION_A@0x12d0000 0x280000 { VBLOCK_A@0x0 0x10000 |