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| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-08 01:31:05 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:21:04 +0200 |
| commit | ced995a89f39c55639a26dce7e2a3e7bf5c2f873 (patch) | |
| tree | d01ddf15dd19e65fc837a9545002b1aabfcfca8a | |
| parent | 71e0ac858e84fc3882fd1f836b95e56df9c933f4 (diff) | |
| download | coreboot-ced995a89f39c55639a26dce7e2a3e7bf5c2f873.tar.xz | |
skylake: clarify and fix gpio macros
The gpio pad configuration currently defaults to ACPI
owned GPIs. A '0' was used which wasn't so clear. Add
a comment and explicitly set it to ACPI. Also,
PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS
macro which causes compliation errors if attempted
to be instantiated. No piece of code tried to use
it so the error was overlooked.
Lastly, allow for soc/gpio.h to be included during
ASL compilation. That allows for gpio_defs.h to be
included and those macros utilized without needing
to know the file name and where it lives; just use
the generic gpio.h.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291935
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 1c462a7964..2116c7efc2 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -21,9 +21,11 @@ #ifndef _SOC_GPIO_H_ #define _SOC_GPIO_H_ +#include <soc/gpio_defs.h> + +#ifndef __ACPI__ #include <stdint.h> #include <stddef.h> -#include <soc/gpio_defs.h> #include <soc/gpio_fsp.h> /* SOC has 8 GPIO communities GPP A~G, GPD */ @@ -99,7 +101,9 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); .dw0 = dw0_, \ } -#define _PAD_CFG(pad_, term_, dw0_) _PAD_CFG_ATTRS(pad_, term_, dw0_, 0) +/* Default to ACPI owned. Ownership only matters for GPI pads. */ +#define _PAD_CFG(pad_, term_, dw0_) \ + _PAD_CFG_ATTRS(pad_, term_, dw0_, PAD_FIELD(HOSTSW, ACPI)) /* Native Function - No Rx buffer manipulation */ #define PAD_CFG_NF(pad_, term_, rst_, func_) \ @@ -131,7 +135,7 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); /* General purpose input routed to SMI. This assumes edge triggered events. */ #define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \ - _PAD_CFG(pad_, term_, \ + _PAD_CFG_ATTRS(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \ NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) @@ -151,4 +155,5 @@ struct pad_config { uint32_t dw0; }; +#endif /* __ACPI__ */ #endif |